Home
last modified time | relevance | path

Searched refs:FSL_FEATURE_SIM_OPT_HAS_TIMESRC (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy_features.h1192 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) macro
DRV32M1_ri5cy_features.h1171 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) macro