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Searched refs:FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy_features.h1220 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) macro
DRV32M1_ri5cy_features.h1199 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) macro