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Searched refs:FIRCDIV (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c36 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV…
37 #define SCG_FIRCDIV_FIRCDIV2_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV…
38 #define SCG_FIRCDIV_FIRCDIV3_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV3_MASK) >> SCG_FIRCDIV_FIRCDIV…
544 SCG->FIRCDIV = in CLOCK_InitFirc()
Dfsl_clock.h1348 uint32_t reg = SCG->FIRCDIV; in CLOCK_SetFircAsyncClkDiv()
1363 SCG->FIRCDIV = reg; in CLOCK_SetFircAsyncClkDiv()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16195 __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ member
DRV32M1_zero_riscy.h17023 __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ member