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Searched refs:FIFO (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpuart.c359 base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); in LPUART_Init()
362 base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); in LPUART_Init()
581 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | in LPUART_EnableInterrupts()
592 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & in LPUART_DisableInterrupts()
604 temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; in LPUART_GetEnabledInterrupts()
616 temp |= (base->FIFO & in LPUART_GetStatusFlags()
628 temp = (uint32_t)base->FIFO; in LPUART_ClearStatusFlags()
631 base->FIFO = temp; in LPUART_ClearStatusFlags()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h12303 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ member
DRV32M1_zero_riscy.h12447 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ member