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Searched refs:EMVSIM_PCSR_SRST_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h5238 #define EMVSIM_PCSR_SRST_MASK (0x8U) macro
5244 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
DRV32M1_zero_riscy.h4509 #define EMVSIM_PCSR_SRST_MASK (0x8U) macro
4515 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)