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Searched refs:EMVSIM_INT_MASK_CWT_ERR_IM_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h4975 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) macro
4981 …(uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
DRV32M1_zero_riscy.h4246 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) macro
4252 …(uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)