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Searched refs:EMVSIM_CTRL_LRC_EN_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h4880 #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) macro
4886 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
DRV32M1_zero_riscy.h4151 #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) macro
4157 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)