Home
last modified time | relevance | path

Searched refs:EMVSIM_CTRL_FLSH_TX_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h4782 #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) macro
4788 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
DRV32M1_zero_riscy.h4053 #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) macro
4059 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)