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Searched refs:EMVSIM0_BASE (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h5366 #define EMVSIM0_BASE (0x40038000u) macro
5368 #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
5370 #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE }
DRV32M1_zero_riscy.h4637 #define EMVSIM0_BASE (0x40038000u) macro
4639 #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
4641 #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE }