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Searched refs:DMA_CSR_INTMAJOR_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_edma.c195 base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; in EDMA_EnableChannelInterrupts()
218 base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; in EDMA_DisableChannelInterrupts()
360 tcd->CSR |= DMA_CSR_INTMAJOR_MASK; in EDMA_TcdEnableInterrupts()
377 tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; in EDMA_TcdDisableInterrupts()
637 handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; in EDMA_SubmitTransfer()
675 handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; in EDMA_SubmitTransfer()
Dfsl_edma.h130 …kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhaus…
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h4454 #define DMA_CSR_INTMAJOR_MASK (0x2U) macro
4460 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
DRV32M1_zero_riscy.h3725 #define DMA_CSR_INTMAJOR_MASK (0x2U) macro
3731 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)