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Searched refs:DMA_CSR_INTHALF_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_edma.c201 base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; in EDMA_EnableChannelInterrupts()
224 base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; in EDMA_DisableChannelInterrupts()
366 tcd->CSR |= DMA_CSR_INTHALF_MASK; in EDMA_TcdEnableInterrupts()
383 tcd->CSR &= ~DMA_CSR_INTHALF_MASK; in EDMA_TcdDisableInterrupts()
Dfsl_edma.h131 …kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to hal…
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h4461 #define DMA_CSR_INTHALF_MASK (0x4U) macro
4467 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
DRV32M1_zero_riscy.h3732 #define DMA_CSR_INTHALF_MASK (0x4U) macro
3738 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)