Home
last modified time | relevance | path

Searched refs:DMA_CSR_ESG_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_edma.c284 tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_TcdSetTransferConfig()
682 csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
693 csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
706 if (tcdRegs->CSR & DMA_CSR_ESG_MASK) in EDMA_SubmitTransfer()
772 if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) in EDMA_StartTransfer()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h4475 #define DMA_CSR_ESG_MASK (0x10U) macro
4481 …) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
DRV32M1_zero_riscy.h3746 #define DMA_CSR_ESG_MASK (0x10U) macro
3752 …) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)