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Searched refs:DMA_CSR_DREQ_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_edma.h459 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); in EDMA_EnableAutoStopRequest()
601 tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); in EDMA_TcdEnableAutoStopRequest()
Dfsl_edma.c284 tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_TcdSetTransferConfig()
635 handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
682 csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
693 csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h4468 #define DMA_CSR_DREQ_MASK (0x8U) macro
4474 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
DRV32M1_zero_riscy.h3739 #define DMA_CSR_DREQ_MASK (0x8U) macro
3745 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)