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Searched refs:DC_RESID_CTRL (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c806 …XCVR_RX_DIG->DC_RESID_CTRL = mode_config->dc_resid_ctrl_init | mode_datarate_config->dc_resid_ctrl… in XCVR_Configure()
809 …XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz; in XCVR_Configure()
811 …XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | mode_datarate_config->dc_resid_ctrl_… in XCVR_Configure()
818 …XCVR_RX_DIG->DC_RESID_CTRL = mode_config->dc_resid_ctrl_init | mode_datarate_config->dc_resid_ctrl… in XCVR_Configure()
821 …XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz; in XCVR_Configure()
823 …XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | mode_datarate_config->dc_resid_ctrl_… in XCVR_Configure()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h27271 __IO uint32_t DC_RESID_CTRL; /**< DC Residual Control, offset: 0x1D4 */ member
DRV32M1_zero_riscy.h26402 __IO uint32_t DC_RESID_CTRL; /**< DC Residual Control, offset: 0x1D4 */ member