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Searched refs:DCOC_CTRL_1 (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr_trim.c117 dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */ in rx_bba_dcoc_dac_trim_shortIQ()
256 XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */ in rx_bba_dcoc_dac_trim_shortIQ()
581 dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ in rx_bba_dcoc_dac_trim_DCest()
746 XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ in rx_bba_dcoc_dac_trim_DCest()
780 dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ in DCOC_DAC_INIT_Cal()
990 XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ in DCOC_DAC_INIT_Cal()
Dfsl_xcvr.c835 …XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | mode_datarate_config->dcoc_ctrl_1_init_2… in XCVR_Configure()
839 …XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz;… in XCVR_Configure()
843 …XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | mode_datarate_config->dcoc_ctrl_1_init … in XCVR_Configure()
852 …XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | mode_datarate_config->dcoc_ctrl_1_init_3… in XCVR_Configure()
856 …XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz;… in XCVR_Configure()
860 …XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | mode_datarate_config->dcoc_ctrl_1_init |… in XCVR_Configure()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h27200 __IO uint32_t DCOC_CTRL_1; /**< DCOC Control 1, offset: 0x28 */ member
DRV32M1_zero_riscy.h26331 __IO uint32_t DCOC_CTRL_1; /**< DCOC Control 1, offset: 0x28 */ member