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Searched refs:DCOC_CTRL_0 (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr_trim.c116 dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */ in rx_bba_dcoc_dac_trim_shortIQ()
129 …XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | X… in rx_bba_dcoc_dac_trim_shortIQ()
133 …XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_M… in rx_bba_dcoc_dac_trim_shortIQ()
255 XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */ in rx_bba_dcoc_dac_trim_shortIQ()
580 dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ in rx_bba_dcoc_dac_trim_DCest()
600 temp = XCVR_RX_DIG->DCOC_CTRL_0; in rx_bba_dcoc_dac_trim_DCest()
606 XCVR_RX_DIG->DCOC_CTRL_0 = temp; in rx_bba_dcoc_dac_trim_DCest()
745 XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ in rx_bba_dcoc_dac_trim_DCest()
779 dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ in DCOC_DAC_INIT_Cal()
812 temp = XCVR_RX_DIG->DCOC_CTRL_0; in DCOC_DAC_INIT_Cal()
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Dfsl_xcvr.c834 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | mode_datarate_config->dcoc_ctrl_0_… in XCVR_Configure()
838 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_… in XCVR_Configure()
842 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_… in XCVR_Configure()
851 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | mode_datarate_config->dcoc_ctrl_0_… in XCVR_Configure()
855 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_… in XCVR_Configure()
859 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_… in XCVR_Configure()
1199 …XCVR_RX_DIG->DCOC_CTRL_0 = (com_config->dcoc_ctrl_0_init_26mhz+XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DU… in XCVR_Configure()
1221 …XCVR_RX_DIG->DCOC_CTRL_0 = (com_config->dcoc_ctrl_0_init_32mhz+XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DU… in XCVR_Configure()
1269 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_… in XCVR_Configure()
1290 …XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_… in XCVR_Configure()
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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h27199 __IO uint32_t DCOC_CTRL_0; /**< DCOC Control 0, offset: 0x24 */ member
DRV32M1_zero_riscy.h26330 __IO uint32_t DCOC_CTRL_0; /**< DCOC Control 0, offset: 0x24 */ member