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Searched refs:DCDCSC (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_spm.h704 …base->DCDCSC = (base->DCDCSC & ~SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK) | SPM_DCDCSC_DCDC_VBAT_DIV_CTR… in SPM_SetDcdcVbatAdcMeasure()
717 base->DCDCSC |= SPM_DCDCSC_PWD_CMP_OFFSET_MASK; in SPM_EnablePowerDownCmpOffset()
721 base->DCDCSC &= ~SPM_DCDCSC_PWD_CMP_OFFSET_MASK; in SPM_EnablePowerDownCmpOffset()
733 return (base->DCDCSC & (SPM_DCDCSC_DCDC_STS_DC_OK_MASK | SPM_DCDCSC_CLKFLT_FAULT_MASK)); in SPM_GetDcdcStatusFlags()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h18651 …__IO uint32_t DCDCSC; /**< DCDC Status Control Register, offset: 0x304 … member
DRV32M1_zero_riscy.h19479 …__IO uint32_t DCDCSC; /**< DCDC Status Control Register, offset: 0x304 … member