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Searched refs:DCDCC2 (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_spm.c124 …base->DCDCC2 &= ~(SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK | SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATAD… in SPM_SetDcdcBattMonitor()
128 base->DCDCC2 |= SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL(batAdcVal); in SPM_SetDcdcBattMonitor()
129 base->DCDCC2 |= SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK; in SPM_SetDcdcBattMonitor()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h18654 __IO uint32_t DCDCC2; /**< DCDC Control Register 2, offset: 0x310 */ member
DRV32M1_zero_riscy.h19482 __IO uint32_t DCDCC2; /**< DCDC Control Register 2, offset: 0x310 */ member