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Searched refs:CnSC (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_tpm.c251 base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &= in TPM_SetupPwm()
255 while ((base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & in TPM_SetupPwm()
261 base->CONTROLS[chnlParams->chnlNumber * 2].CnSC |= in TPM_SetupPwm()
265 while (!(base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & in TPM_SetupPwm()
273 base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &= in TPM_SetupPwm()
277 while ((base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & in TPM_SetupPwm()
283 base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC |= in TPM_SetupPwm()
287 while (!(base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & in TPM_SetupPwm()
313 base->CONTROLS[chnlParams->chnlNumber].CnSC &= in TPM_SetupPwm()
317 while ((base->CONTROLS[chnlParams->chnlNumber].CnSC & in TPM_SetupPwm()
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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19266 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
DRV32M1_zero_riscy.h20094 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member