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Searched refs:CTRL (Results 1 – 19 of 19) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpuart.c186 uint32_t ctrl = base->CTRL; in LPUART_ReadNonBlocking()
287 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); in LPUART_Init()
310 temp = base->CTRL & in LPUART_Init()
338 base->CTRL = temp; in LPUART_Init()
405 temp = base->CTRL; in LPUART_Init()
416 base->CTRL = temp; in LPUART_Init()
450 base->CTRL = 0; in LPUART_Deinit()
543 oldCtrl = base->CTRL; in LPUART_SetBaudRate()
546 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); in LPUART_SetBaudRate()
566 base->CTRL = oldCtrl; in LPUART_SetBaudRate()
[all …]
Dfsl_lpuart.h494 base->CTRL |= LPUART_CTRL_TIE_MASK; in LPUART_EnableTxDMA()
499 base->CTRL &= ~LPUART_CTRL_TIE_MASK; in LPUART_EnableTxDMA()
516 base->CTRL |= LPUART_CTRL_RIE_MASK; in LPUART_EnableRxDMA()
521 base->CTRL &= ~LPUART_CTRL_RIE_MASK; in LPUART_EnableRxDMA()
545 base->CTRL |= LPUART_CTRL_TE_MASK; in LPUART_EnableTx()
549 base->CTRL &= ~LPUART_CTRL_TE_MASK; in LPUART_EnableTx()
565 base->CTRL |= LPUART_CTRL_RE_MASK; in LPUART_EnableRx()
569 base->CTRL &= ~LPUART_CTRL_RE_MASK; in LPUART_EnableRx()
599 uint32_t ctrl = base->CTRL; in LPUART_ReadByte()
Dfsl_lpadc.h343 base->CTRL |= ADC_CTRL_ADCEN_MASK; in LPADC_Enable()
347 base->CTRL &= ~ADC_CTRL_ADCEN_MASK; in LPADC_Enable()
358 base->CTRL |= ADC_CTRL_RSTFIFO_MASK; in LPADC_DoResetFIFO()
370 base->CTRL |= ADC_CTRL_RST_MASK; in LPADC_DoResetConfig()
371 base->CTRL &= ~ADC_CTRL_RST_MASK; in LPADC_DoResetConfig()
Dfsl_crc.c108 base->CTRL = crcControl; in CRC_ConfigureAndStart()
114 base->CTRL = crcControl | CRC_CTRL_WAS(true); in CRC_ConfigureAndStart()
120 base->CTRL = crcControl; in CRC_ConfigureAndStart()
245 totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; in CRC_Get16bitResult()
Dfsl_ewm.h164 base->CTRL |= mask; in EWM_EnableInterrupts()
179 base->CTRL &= ~mask; in EWM_DisableInterrupts()
199 return (base->CTRL & EWM_CTRL_EWMEN_MASK); in EWM_GetStatusFlags()
Dfsl_flexio.c71 ctrlReg = base->CTRL; in FLEXIO_Init()
80 base->CTRL = ctrlReg; in FLEXIO_Init()
104 base->CTRL |= FLEXIO_CTRL_SWRST_MASK; in FLEXIO_Reset()
105 base->CTRL = 0; in FLEXIO_Reset()
Dfsl_flexio_i2c_master.h186 base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_I2C_MasterEnable()
190 base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_I2C_MasterEnable()
Dfsl_flexio_uart.h326 base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_UART_Enable()
330 base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_UART_Enable()
Dfsl_flexio_spi.h443 base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_SPI_Enable()
447 base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_SPI_Enable()
Dfsl_flexio.h362 base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_Enable()
366 base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; in FLEXIO_Enable()
Dfsl_flexio_spi.c163 ctrlReg = base->flexioBase->CTRL; in FLEXIO_SPI_MasterInit()
172 base->flexioBase->CTRL = ctrlReg; in FLEXIO_SPI_MasterInit()
309 ctrlReg = base->flexioBase->CTRL; in FLEXIO_SPI_SlaveInit()
318 base->flexioBase->CTRL = ctrlReg; in FLEXIO_SPI_SlaveInit()
Dfsl_lpadc.c74 base->CTRL &= ~ADC_CTRL_DOZEN_MASK; in LPADC_Init()
78 base->CTRL |= ADC_CTRL_DOZEN_MASK; in LPADC_Init()
Dfsl_ewm.c39 base->CTRL = value; in EWM_Init()
Dfsl_flexio_uart.c118 ctrlReg = base->flexioBase->CTRL; in FLEXIO_UART_Init()
127 base->flexioBase->CTRL = ctrlReg; in FLEXIO_UART_Init()
Dfsl_flexio_i2c_master.c447 controlVal = base->flexioBase->CTRL; in FLEXIO_I2C_MasterInit()
457 base->flexioBase->CTRL = controlVal; in FLEXIO_I2C_MasterInit()
Dfsl_clock.c258 USBVREG->CTRL |= USBVREG_CTRL_EN_MASK; in CLOCK_EnableUsbfs0Clock()
/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c1027 XCVR_TSM->CTRL = com_config->tsm_ctrl; in XCVR_Configure()
1032 XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK; in XCVR_Configure()
1354 XCVR_TX_DIG->CTRL = com_config->tx_ctrl; in XCVR_Configure()
1831 XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK; in XCVR_ForceRxWu()
1836 XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK; in XCVR_ForceRxWd()
1841 XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; in XCVR_ForceTxWu()
1846 XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; in XCVR_ForceTxWd()
1863 temp = XCVR_TX_DIG->CTRL; in XCVR_DftTxCW()
1866 XCVR_TX_DIG->CTRL = temp; in XCVR_DftTxCW()
1937 temp = XCVR_TX_DIG->CTRL; in XCVR_DftTxPatternReg()
[all …]
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy.h623 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ member
2367 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ member
3934 __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ member
5075 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ member
5492 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ member
12443 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ member
14460 __I uint32_t CTRL; /**< DWT Control Register, offset: 0x0 */ member
22408 __IO uint32_t CTRL; /**< USB VREG Control Register, offset: 0x0 */ member
28304 __IO uint32_t CTRL; /**< TSM CONTROL, offset: 0x0 */ member
30074 __IO uint32_t CTRL; /**< TX Digital Control, offset: 0x0 */ member
DRV32M1_ri5cy.h652 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ member
2584 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ member
4663 __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ member
5804 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ member
6130 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ member
12299 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ member
21580 __IO uint32_t CTRL; /**< USB VREG Control Register, offset: 0x0 */ member
29173 __IO uint32_t CTRL; /**< TSM CONTROL, offset: 0x0 */ member
30943 __IO uint32_t CTRL; /**< TX Digital Control, offset: 0x0 */ member