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Searched refs:CSR (Results 1 – 13 of 13) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lptmr.h179 uint32_t reg = base->CSR; in LPTMR_EnableInterrupts()
184 base->CSR = reg; in LPTMR_EnableInterrupts()
196 uint32_t reg = base->CSR; in LPTMR_DisableInterrupts()
201 base->CSR = reg; in LPTMR_DisableInterrupts()
214 return (base->CSR & LPTMR_CSR_TIE_MASK); in LPTMR_GetEnabledInterrupts()
230 base->CSR |= LPTMR_CSR_TDRE_MASK; in LPTMR_EnableTimerDMA()
234 base->CSR &= ~(LPTMR_CSR_TDRE_MASK); in LPTMR_EnableTimerDMA()
254 return (base->CSR & LPTMR_CSR_TCF_MASK); in LPTMR_GetStatusFlags()
266 base->CSR |= mask; in LPTMR_ClearStatusFlags()
335 uint32_t reg = base->CSR; in LPTMR_StartTimer()
[all …]
Dfsl_edma.c85 base->TCD[channel].CSR = 0; in EDMA_InstallTCD()
86 base->TCD[channel].CSR = tcd->CSR; in EDMA_InstallTCD()
169 … base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); in EDMA_SetBandWidth()
195 base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; in EDMA_EnableChannelInterrupts()
201 base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; in EDMA_EnableChannelInterrupts()
218 base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; in EDMA_DisableChannelInterrupts()
224 base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; in EDMA_DisableChannelInterrupts()
244 tcd->CSR = DMA_CSR_DREQ(true); in EDMA_TcdReset()
284 tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; in EDMA_TcdSetTransferConfig()
329 tcd->CSR |= DMA_CSR_MAJORELINK_MASK; in EDMA_TcdSetChannelLink()
[all …]
Dfsl_mmdvsq.c19 temp = base->CSR; in MMDVSQ_GetDivideRemainder()
24 base->CSR = temp; in MMDVSQ_GetDivideRemainder()
30 base->CSR |= MMDVSQ_CSR_SRT_MASK; in MMDVSQ_GetDivideRemainder()
40 temp = base->CSR; in MMDVSQ_GetDivideQuotient()
45 base->CSR = temp; in MMDVSQ_GetDivideQuotient()
51 base->CSR |= MMDVSQ_CSR_SRT_MASK; in MMDVSQ_GetDivideQuotient()
Dfsl_mmdvsq.h116 return (mmdvsq_execution_status_t)(base->CSR >> MMDVSQ_CSR_SQRT_SHIFT); in MMDVSQ_GetExecutionStatus()
137 base->CSR |= MMDVSQ_CSR_DFS_MASK; in MMDVSQ_SetFastStartConfig()
141 base->CSR &= ~MMDVSQ_CSR_DFS_MASK; in MMDVSQ_SetFastStartConfig()
162 base->CSR |= MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
166 base->CSR &= ~MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
Dfsl_edma.h216 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
459 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); in EDMA_EnableAutoStopRequest()
572 tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); in EDMA_TcdSetBandWidth()
601 tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); in EDMA_TcdEnableAutoStopRequest()
Dfsl_lptmr.c86 base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | in LPTMR_Init()
97 base->CSR &= ~LPTMR_CSR_TEN_MASK; in LPTMR_Deinit()
Dfsl_lpcmp.h285 return base->CSR; in LPCMP_GetStatusFlags()
296 base->CSR = mask; in LPCMP_ClearStatusFlags()
Dfsl_clock.c29 #define SCG_CSR_SCS_VAL ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
Dfsl_clock.h1072 *(uint32_t *)config = SCG->CSR; in CLOCK_GetCurSysClkConfig()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c395 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; in SystemCoreClockUpdate()
397 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
Dsystem_RV32M1_ri5cy.c392 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; in SystemCoreClockUpdate()
394 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
DRV32M1_zero_riscy.h2661 …__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C… member
9782 __IO uint32_t CSR; /**< Comparator Status Register, offset: 0x20 */ member
12263 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
13423 __IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */ member
17009 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ member
DRV32M1_ri5cy.h2886 …__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C… member
9638 __IO uint32_t CSR; /**< Comparator Status Register, offset: 0x20 */ member
12119 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
16181 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ member