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Searched refs:CS (Results 1 – 6 of 6) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_wdog32.h195 base->CS |= WDOG_CS_EN_MASK; in WDOG32_Enable()
209 base->CS &= ~WDOG_CS_EN_MASK; in WDOG32_Disable()
226 base->CS |= mask; in WDOG32_EnableInterrupts()
243 base->CS &= ~mask; in WDOG32_DisableInterrupts()
263 return (base->CS & (WDOG_CS_EN_MASK | WDOG_CS_FLG_MASK)); in WDOG32_GetStatusFlags()
325 if ((base->CS) & WDOG_CS_CMD32EN_MASK) in WDOG32_Unlock()
346 if ((base->CS) & WDOG_CS_CMD32EN_MASK) in WDOG32_Refresh()
Dfsl_wdog32.c19 base->CS |= WDOG_CS_FLG_MASK; in WDOG32_ClearStatusFlags()
60 base->CS = value; in WDOG32_Init()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c366 WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; in SystemInit()
Dsystem_RV32M1_ri5cy.c363 WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; in SystemInit()
DRV32M1_ri5cy.h5903 } CS[6]; member
23062 …__IO uint32_t CS; /**< Watchdog Control and Status Register, offset… member
DRV32M1_zero_riscy.h5174 } CS[6]; member
23890 …__IO uint32_t CS; /**< Watchdog Control and Status Register, offset… member