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Searched refs:CLRTEN (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpit.h349 base->CLRTEN |= (LPIT_CLRTEN_CLR_T_EN_0_MASK << channel); in LPIT_StopTimer()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h11203 __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ member
DRV32M1_zero_riscy.h11347 __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ member