Home
last modified time | relevance | path

Searched refs:CFGR1 (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpspi.h709 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); in LPSPI_SetMasterSlaveMode()
720 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); in LPSPI_IsMaster()
767 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); in LPSPI_SetAllPcsPolarity()
Dfsl_lpspi.c195 …base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOS… in LPSPI_MasterInit()
263 base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | in LPSPI_SlaveInit()
329 cfgr1Value = base->CFGR1 & ~(1U << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); in LPSPI_SetOnePcsPolarity()
332 base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); in LPSPI_SetOnePcsPolarity()
657 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_MasterTransferBlocking()
820 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_MasterTransferNonBlocking()
Dfsl_lpspi_edma.c235 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_MasterTransferEDMA()
686 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_SlaveTransferEDMA()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h11541 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DRV32M1_zero_riscy.h11685 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member