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Searched refs:CFG (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpadc.c101 base->CFG = tmp32; in LPADC_Init()
283 base->CFG |= ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
287 base->CFG &= ~ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h656 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ member
DRV32M1_zero_riscy.h627 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ member