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Searched refs:CCR1 (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpcmp.h209 base->CCR1 |= LPCMP_CCR1_DMA_EN_MASK; in LPCMP_EnableDMA()
213 base->CCR1 &= ~LPCMP_CCR1_DMA_EN_MASK; in LPCMP_EnableDMA()
230 base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; in LPCMP_EnableWindowMode()
234 base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; in LPCMP_EnableWindowMode()
Dfsl_lpcmp.c79 …tmp32 = base->CCR1 & ~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_M… in LPCMP_Init()
92 base->CCR1 = tmp32; in LPCMP_Init()
137 …tmp32 = base->CCR1 & ~(LPCMP_CCR1_FILT_PER_MASK | LPCMP_CCR1_FILT_CNT_MASK | LPCMP_CCR1_SAMPLE_EN_… in LPCMP_SetFilterConfig()
143 base->CCR1 = tmp32; in LPCMP_SetFilterConfig()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h9633 …__IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ member
DRV32M1_zero_riscy.h9777 …__IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ member