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Searched refs:CCR0 (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpcmp.h178 base->CCR0 |= LPCMP_CCR0_CMP_EN_MASK; in LPCMP_Enable()
182 base->CCR0 &= ~LPCMP_CCR0_CMP_EN_MASK; in LPCMP_Enable()
Dfsl_lpcmp.c72 base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK; in LPCMP_Init()
76 base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; in LPCMP_Init()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h9632 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member
DRV32M1_zero_riscy.h9776 …__IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ member