Searched refs:CCR (Results 1 – 5 of 5) sorted by relevance
116 uint32_t reg = base->CCR; in MU_BootCoreB()120 base->CCR = reg; in MU_BootCoreB()150 uint32_t ccr = base->CCR & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK); in MU_HardwareResetOtherCore()164 base->CCR = ccr | MU_CCR_HR_MASK; in MU_HardwareResetOtherCore()180 base->CCR = ccr; in MU_HardwareResetOtherCore()
491 base->CCR |= MU_CCR_RSTH_MASK; in MU_HoldCoreBReset()564 base->CCR |= MU_CCR_HRM_MASK; in MU_MaskHardwareReset()568 base->CCR &= ~MU_CCR_HRM_MASK; in MU_MaskHardwareReset()629 base->CCR |= MU_CCR_CLKE_MASK; in MU_SetClockOnOtherCoreEnable()633 base->CCR &= ~MU_CCR_CLKE_MASK; in MU_SetClockOnOtherCoreEnable()
400 base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); in LPSPI_MasterSetBaudRate()415 base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); in LPSPI_MasterSetDelayScaler()419 base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); in LPSPI_MasterSetDelayScaler()423 base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); in LPSPI_MasterSetDelayScaler()
11546 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member14048 __IO uint32_t CCR; /**< Core Control Register, offset: 0x68 */ member
11690 …__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ member14730 __IO uint32_t CCR; /**< Core Control Register, offset: 0x68 */ member
