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Searched refs:CAU3_SR_MDISF_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h1860 #define CAU3_SR_MDISF_MASK (0x80000000U) macro
1866 … (((uint32_t)(((uint32_t)(x)) << CAU3_SR_MDISF_SHIFT)) & CAU3_SR_MDISF_MASK)
DRV32M1_zero_riscy.h1643 #define CAU3_SR_MDISF_MASK (0x80000000U) macro
1649 … (((uint32_t)(((uint32_t)(x)) << CAU3_SR_MDISF_SHIFT)) & CAU3_SR_MDISF_MASK)