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Searched refs:CAU3_SEMA4_NS_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h2017 #define CAU3_SEMA4_NS_MASK (0x80U) macro
2023 … (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_NS_SHIFT)) & CAU3_SEMA4_NS_MASK)
DRV32M1_zero_riscy.h1800 #define CAU3_SEMA4_NS_MASK (0x80U) macro
1806 … (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_NS_SHIFT)) & CAU3_SEMA4_NS_MASK)