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Searched refs:CAU3_DBGCSR_DDBGMC_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_cau3.c997 base->DBGCSR = CAU3_DBGCSR_DDBGMC_MASK; /* set DBGCSR[DDBGMC] */ in CAU3_MakeMemsPrivate()
Dfsl_cau3_ble.c731 base->DBGCSR = CAU3_DBGCSR_DDBGMC_MASK; /* set DBGCSR[DDBGMC] */ in CAU3_MakeMemsPrivate()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h1878 #define CAU3_DBGCSR_DDBGMC_MASK (0x2U) macro
1884 … (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBGMC_SHIFT)) & CAU3_DBGCSR_DDBGMC_MASK)
DRV32M1_zero_riscy.h1661 #define CAU3_DBGCSR_DDBGMC_MASK (0x2U) macro
1667 … (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBGMC_SHIFT)) & CAU3_DBGCSR_DDBGMC_MASK)