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Searched refs:CAU3_CC_CF_V_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h2110 #define CAU3_CC_CF_V_MASK (0x2U) macro
2112 … (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_V_SHIFT)) & CAU3_CC_CF_V_MASK)
DRV32M1_zero_riscy.h1893 #define CAU3_CC_CF_V_MASK (0x2U) macro
1895 … (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_V_SHIFT)) & CAU3_CC_CF_V_MASK)