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Searched refs:ATTR (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_edma.c77 base->TCD[channel].ATTR = tcd->ATTR; in EDMA_InstallTCD()
178 tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); in EDMA_SetModulo()
179 base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); in EDMA_SetModulo()
236 tcd->ATTR = 0U; in EDMA_TcdReset()
260 tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); in EDMA_TcdSetTransferConfig()
349 tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); in EDMA_TcdSetModulo()
350 tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); in EDMA_TcdSetModulo()
501 tcdRegs->ATTR = 0; in EDMA_CreateHandle()
Dfsl_edma.h209 __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ member
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h2872 …__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x100… member
DRV32M1_zero_riscy.h2647 …__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x100… member