Searched refs:AGC_CTRL_1 (Results 1 – 4 of 4) sorted by relevance
119 agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */ in rx_bba_dcoc_dac_trim_shortIQ()125 …XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK… in rx_bba_dcoc_dac_trim_shortIQ()126 …XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK… in rx_bba_dcoc_dac_trim_shortIQ()135 …XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER… in rx_bba_dcoc_dac_trim_shortIQ()259 XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */ in rx_bba_dcoc_dac_trim_shortIQ()583 agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ in rx_bba_dcoc_dac_trim_DCest()594 …XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ in rx_bba_dcoc_dac_trim_DCest()749 XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ in rx_bba_dcoc_dac_trim_DCest()782 agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ in DCOC_DAC_INIT_Cal()806 …XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ in DCOC_DAC_INIT_Cal()[all …]
932 …XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | mode_datarate_config->agc_ctrl_1_ini… in XCVR_Configure()937 …XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26m… in XCVR_Configure()945 …XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | mode_datarate_config->agc_ctrl_1_ini… in XCVR_Configure()951 …XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32m… in XCVR_Configure()
27192 __IO uint32_t AGC_CTRL_1; /**< AGC Control 1, offset: 0x8 */ member
26323 __IO uint32_t AGC_CTRL_1; /**< AGC Control 1, offset: 0x8 */ member
