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Searched refs:__IO (Results 1 – 6 of 6) sorted by relevance

/hal_openisa-3.5.0-3.4.0/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h652 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
653 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
654 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
655 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
656 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
657 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
659 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
662 __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
664 …__IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xC0…
667 …__IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offse…
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DRV32M1_zero_riscy.h623 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
624 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
625 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
626 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
627 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
628 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
630 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
633 __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
635 …__IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xC0…
638 …__IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offse…
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/hal_openisa-3.5.0-3.4.0/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_edma.h207 __IO uint32_t SADDR; /*!< SADDR register, used to save source address */
208 __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */
209 __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */
210 __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */
211 __IO uint32_t SLAST; /*!< SLAST register */
212 __IO uint32_t DADDR; /*!< DADDR register, used for destination address */
213 __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */
214 …__IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loo…
215 … __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */
216 __IO uint16_t CSR; /*!< CSR register, for TCD control status */
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Dfsl_cau3.c2195 __IO uint32_t *pka = base->PKA0; in cau3_pkha_write_word()
2196 __IO uint32_t *pkb = base->PKB0; in cau3_pkha_write_word()
2197 __IO uint32_t *pkn = base->PKN0; in cau3_pkha_write_word()
2225 __IO uint32_t *pka = base->PKA0; in cau3_pkha_read_word()
2226 __IO uint32_t *pkb = base->PKB0; in cau3_pkha_read_word()
2227 __IO uint32_t *pkn = base->PKN0; in cau3_pkha_read_word()
Dfsl_cau3_ble.c2390 __IO uint32_t *pka = base->PKA0; in cau3_pkha_write_word()
2391 __IO uint32_t *pkb = base->PKB0; in cau3_pkha_write_word()
2392 __IO uint32_t *pkn = base->PKN0; in cau3_pkha_write_word()
2420 __IO uint32_t *pka = base->PKA0; in cau3_pkha_read_word()
2421 __IO uint32_t *pkb = base->PKB0; in cau3_pkha_read_word()
2422 __IO uint32_t *pkn = base->PKN0; in cau3_pkha_read_word()
/hal_openisa-3.5.0-3.4.0/vega_sdk_riscv/RISCV/
Dcore_riscv32.h112 #define __IO volatile /*!< Defines 'read / write' permissions */ macro