1 /*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
19 specific prior written permission.
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
33
34 #ifndef __CORE_RISCV32_H__
35 #define __CORE_RISCV32_H__
36
37 #include <stdint.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #define RISCV32
44
45 #if defined ( __GNUC__ )
46 #define __ASM __asm /*!< asm keyword for GNU Compiler */
47 #define __INLINE inline /*!< inline keyword for GNU Compiler */
48 #define __STATIC_INLINE static inline
49
50 #else
51 #error Unknown compiler
52 #endif
53
54 #if defined ( __GNUC__ )
55
56 #define __BKPT(x) __ASM("ebreak")
57
__NOP(void)58 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
59 {
60 __ASM volatile ("nop");
61 }
62
__DSB(void)63 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
64 {
65 __ASM volatile ("nop");
66 }
67
__ISB(void)68 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
69 {
70 __ASM volatile ("nop");
71 }
72
__WFI(void)73 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
74 {
75 __ASM volatile ("wfi");
76 }
77
__WFE(void)78 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
79 {
80 }
81
__enable_irq(void)82 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
83 {
84 __ASM volatile ("csrsi mstatus, 8");
85 }
86
__disable_irq(void)87 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
88 {
89 __ASM volatile ("csrci mstatus, 8");
90 }
91
__REV(uint32_t value)92 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
93 {
94 return __builtin_bswap32(value);
95 }
96
__REV16(uint32_t value)97 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
98 {
99 return __builtin_bswap16(value);
100 }
101
102 #else
103 #error Unknown compiler
104 #endif
105
106 #ifdef __cplusplus
107 #define __I volatile /*!< Defines 'read only' permissions */
108 #else
109 #define __I volatile const /*!< Defines 'read only' permissions */
110 #endif
111 #define __O volatile /*!< Defines 'write only' permissions */
112 #define __IO volatile /*!< Defines 'read / write' permissions */
113
114 /* following defines should be used for structure members */
115 #define __IM volatile const /*! Defines 'read only' structure member permissions */
116 #define __OM volatile /*! Defines 'write only' structure member permissions */
117 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
118
119 #ifdef __cplusplus
120 }
121 #endif
122
123 #endif /* __CORE_RISCV32_H__ */
124
