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/hal_openisa-3.5.0-3.4.0/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy.h620 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
621 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
644 …__I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300…
1177 …__I uint16_t BLE_PART_ID; /**< BLUETOOTH LOW ENERGY PART ID, offset: 0x600 …
1179 __I uint16_t DSM_STATUS; /**< BLE DSM STATUS, offset: 0x604 */
1183 __I uint16_t BLE_FSM; /**< BLE STATE MACHINE STATUS, offset: 0x60C */
1288 __I uint32_t PCT; /**< Processor Core Type, offset: 0x0 */
1289 __I uint32_t MCFG; /**< Memory Configuration, offset: 0x4 */
1302 …__I uint32_t SMOWNR; /**< Semaphore Ownership Register, offset: 0xF4 */
1311 __I uint32_t CC_CF; /**< Condition Flag, offset: 0x208 */
[all …]
DRV32M1_ri5cy.h649 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
650 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
673 …__I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300…
1505 __I uint32_t PCT; /**< Processor Core Type, offset: 0x0 */
1506 __I uint32_t MCFG; /**< Memory Configuration, offset: 0x4 */
1519 …__I uint32_t SMOWNR; /**< Semaphore Ownership Register, offset: 0xF4 */
1528 __I uint32_t CC_CF; /**< Condition Flag, offset: 0x208 */
1538 __I uint32_t ESTA; /**< Error Status Register, offset: 0x44C */
1548 __I uint32_t PKHA_VID1; /**< PKHA Revision ID 1, offset: 0x4F0 */
1549 __I uint32_t PKHA_VID2; /**< PKHA Revision ID 2, offset: 0x4F4 */
[all …]
/hal_openisa-3.5.0-3.4.0/vega_sdk_riscv/RISCV/
Dcore_riscv32.h107 #define __I volatile /*!< Defines 'read only' permissions */ macro
109 #define __I volatile const /*!< Defines 'read only' permissions */ macro