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Searched refs:uint16_t (Results 1 – 25 of 1861) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_FLEXRAY.h81 __I uint16_t MVR; /**< Module Version, offset: 0x0 */
82 __IO uint16_t MCR; /**< Module Configuration, offset: 0x2 */
83 …__IO uint16_t SYMBADHR; /**< System Memory Base Address High, offset: 0x4…
84 …__IO uint16_t SYMBADLR; /**< System Memory Base Address Low, offset: 0x6 …
85 __IO uint16_t STBSCR; /**< Strobe Signal Control, offset: 0x8 */
87 __IO uint16_t MBDSR; /**< MB Data Size, offset: 0xC */
88 …__IO uint16_t MBSSUTR; /**< MB Segment Size and Utilization, offset: 0xE…
89 __IO uint16_t PEDRAR; /**< PE DRAM Access, offset: 0x10 */
90 __IO uint16_t PEDRDR; /**< PE DRAM Data, offset: 0x12 */
91 __IO uint16_t POCR; /**< Protocol Operation Control, offset: 0x14 */
[all …]
DS32Z2_CTU.h80 …__IO uint16_t TGSCR; /**< Trigger Generator Subunit Control Register, …
81 …__IO uint16_t TCR[CTU_TCR_COUNT]; /**< Trigger Compare Register, array offset: 0x6,…
82 …__IO uint16_t TGSCCR; /**< TGS Counter Compare Register, offset: 0x16 */
83 __IO uint16_t TGSCRR; /**< TGS Counter Reload Register, offset: 0x18 */
90 …__IO uint16_t A[CTU_CLR_COUNT]; /**< Commands List Register A for ADC single-conv…
91 …__IO uint16_t B[CTU_CLR_COUNT]; /**< Command List Register B for ADC dual-convers…
94 __IO uint16_t FDCR; /**< FIFO DMA Control Register, offset: 0x6C */
104 __IO uint16_t EFR; /**< Error Flag Register, offset: 0xC0 */
105 __IO uint16_t IFR; /**< Interrupt Flag Register, offset: 0xC2 */
106 __IO uint16_t IR; /**< Interrupt/DMA Register, offset: 0xC4 */
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DS32Z2_SIUL2.h458 …__IO uint16_t PGPDO1; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
459 …__IO uint16_t PGPDO0; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
460 …__IO uint16_t PGPDO3; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
461 …__IO uint16_t PGPDO2; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
462 …__IO uint16_t PGPDO5; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
463 …__IO uint16_t PGPDO4; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
464 …__IO uint16_t PGPDO7; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
465 …__IO uint16_t PGPDO6; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
466 …__IO uint16_t PGPDO9; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
467 …__IO uint16_t PGPDO8; /**< SIUL2 Parallel GPIO Pad Data Out, offset: 0x…
[all …]
DS32Z2_NETC_F3_PCI_HDR_TYPE0.h78 __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */
79 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
92 …__I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x…
93 __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */
97 …__I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset:…
98 …__I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42…
100 …__IO uint16_t PCI_CFC_PCIE_DEV_CTL; /**< PCI PCIe device control register, offset: 0x…
101 …__I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4…
104 …__I uint16_t PCI_CFC_PCIE_DEV_CTL2; /**< PCI PCIe device control 2 register, offset: …
106 …__I uint16_t PCI_CFC_MSIX_CAP_LIST; /**< PCI MSI-X capabilities list register, offset…
[all …]
DS32Z2_NETC_F0_PCI_HDR_TYPE0.h77 __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */
78 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
91 …__I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x…
92 __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */
96 …__I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset:…
97 …__I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42…
99 …__IO uint16_t PCI_CFC_PCIE_DEV_CTL; /**< PCI PCIe device control register, offset: 0x…
100 …__I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4…
103 …__I uint16_t PCI_CFC_PCIE_DEV_CTL2; /**< PCI PCIe device control 2 register, offset: …
105 …__I uint16_t PCI_CFC_MSIX_CAP_LIST; /**< PCI MSI-X capabilities list register, offset…
[all …]
DS32Z2_NETC_F1_PCI_HDR_TYPE0.h77 __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */
78 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
91 …__I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x…
92 __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */
96 …__I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset:…
97 …__I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42…
99 …__IO uint16_t PCI_CFC_PCIE_DEV_CTL; /**< PCI PCIe device control register, offset: 0x…
100 …__I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4…
103 …__I uint16_t PCI_CFC_PCIE_DEV_CTL2; /**< PCI PCIe device control 2 register, offset: …
105 …__I uint16_t PCI_CFC_MSIX_CAP_LIST; /**< PCI MSI-X capabilities list register, offset…
[all …]
DS32Z2_NETC_F2_PCI_HDR_TYPE0.h77 __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */
78 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */
91 …__I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x…
92 __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */
96 …__I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset:…
97 …__I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42…
99 …__IO uint16_t PCI_CFC_PCIE_DEV_CTL; /**< PCI PCIe device control register, offset: 0x…
100 …__I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4…
103 …__I uint16_t PCI_CFC_PCIE_DEV_CTL2; /**< PCI PCIe device control 2 register, offset: …
105 …__I uint16_t PCI_CFC_MSIX_CAP_LIST; /**< PCI MSI-X capabilities list register, offset…
[all …]
DS32Z2_EDMA4_TCD.h83 …__IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x…
86 …__IO uint16_t SOFF; /**< TCD Signed Source Address Offset Register, a…
87 …__IO uint16_t ATTR; /**< TCD Transfer Attributes Register, array offs…
94 …__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset Regist…
96 …__IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Cha…
97 …__IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Cha…
100 …__IO uint16_t CSR; /**< TCD Control and Status Register, array offse…
102 …__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop C…
103 …__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop C…
287 #define EDMA4_TCD_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CH_MATTR…
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DS32Z2_EDMA3_TCD.h84 …__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offs…
85 …__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x26,…
92 …__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array…
94 …__IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Cha…
95 …__IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Cha…
98 …__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x3C, …
100 …__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop C…
101 …__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop C…
295 #define EDMA3_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_SOFF_SOF…
304 #define EDMA3_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_ATTR_DSI…
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DS32Z2_FEED_DMA_TCD.h84 …__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offs…
85 …__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x26,…
92 …__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array…
94 …__IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Cha…
95 …__IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Cha…
98 …__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x3C, …
100 …__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop C…
101 …__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop C…
279 #define FEED_DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_SOFF_…
288 #define FEED_DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_ATTR_…
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DS32Z2_RESULT_DMA_TCD.h84 …__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offs…
85 …__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x26,…
92 …__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array…
94 …__IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Cha…
95 …__IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Cha…
98 …__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x3C, …
100 …__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop C…
101 …__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop C…
279 #define RESULT_DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << RESULT_DMA_TCD_SOF…
288 #define RESULT_DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << RESULT_DMA_TCD_ATT…
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/hal_nxp-latest/mcux/mcux-sdk/components/slcd_engine/GDH-1247WP/
DGDH-1247WP.c34 static const uint16_t SLCD_NumPos1_Num0[] = {
39 static const uint16_t SLCD_NumPos1_Num1[] = {
44 static const uint16_t SLCD_NumPos1_Num2[] = {
49 static const uint16_t SLCD_NumPos1_Num3[] = {
54 static const uint16_t SLCD_NumPos1_Num4[] = {
59 static const uint16_t SLCD_NumPos1_Num5[] = {
64 static const uint16_t SLCD_NumPos1_Num6[] = {
69 static const uint16_t SLCD_NumPos1_Num7[] = {
74 static const uint16_t SLCD_NumPos1_Num8[] = {
79 static const uint16_t SLCD_NumPos1_Num9[] = {
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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Include/
Darm_nnfunctions.h296 const uint16_t dim_im_in,
297 const uint16_t ch_im_in,
299 const uint16_t ch_im_out,
300 const uint16_t dim_kernel,
301 const uint16_t padding,
302 const uint16_t stride,
304 const uint16_t bias_shift,
305 const uint16_t out_shift,
307 const uint16_t dim_im_out,
336 const uint16_t dim_im_in_x,
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/hal_nxp-latest/mcux/mcux-sdk/drivers/hsadc/
Dfsl_hsadc.c23 #define HSADC_ZXCTRL_ZCE_MASK(index) ((uint16_t)3U << (2U * ((uint16_t)(index))))
24 #define HSADC_ZXCTRL_ZCE(index, value) (uint16_t)(((uint16_t)(value)) << (2U * ((uint16_t)(index))))
26 #define HSADC_CLIST_SAMPLE_MASK(index) ((uint16_t)0xFU << (4U * ((uint16_t)(index))))
27 #define HSADC_CLIST_SAMPLE(index, value) (uint16_t)(((uint16_t)(value)) << (4U * ((uint16_t)(index)…
52 uint16_t channelNumber,
53 uint16_t muxNumber,
104 uint16_t tmp16; in HSADC_Init()
112 tmp16 = (uint16_t)(base->CTRL1 & ~HSADC_CTRL1_SMODE_MASK); in HSADC_Init()
117 tmp16 = (uint16_t)(base->CTRL2 & ~HSADC_CTRL2_SIMULT_MASK); in HSADC_Init()
125 tmp16 = (uint16_t)(base->CTRL3 & ~(HSADC_CTRL3_ADCRES_MASK | HSADC_CTRL3_DMASRC_MASK)); in HSADC_Init()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_DMA_TCD.h80 …__IO uint16_t TCD0_SOFF; /**< TCD Signed Source Address Offset, offset: 0x…
81 __IO uint16_t TCD0_ATTR; /**< TCD Transfer Attributes, offset: 0x26 */
88 …__IO uint16_t TCD0_DOFF; /**< TCD Signed Destination Address Offset, offse…
90 …__IO uint16_t TCD0_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Cha…
91 …__IO uint16_t TCD0_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Cha…
94 __IO uint16_t TCD0_CSR; /**< TCD Control and Status, offset: 0x3C */
96 …__IO uint16_t TCD0_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop C…
97 …__IO uint16_t TCD0_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop C…
107 …__IO uint16_t TCD1_SOFF; /**< TCD Signed Source Address Offset, offset: 0x…
108 __IO uint16_t TCD1_ATTR; /**< TCD Transfer Attributes, offset: 0x4026 */
[all …]
DS32K344_SIUL2.h545 …__IO uint16_t PGPDO1; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
546 …__IO uint16_t PGPDO0; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
547 …__IO uint16_t PGPDO3; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
548 …__IO uint16_t PGPDO2; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
549 …__IO uint16_t PGPDO5; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
550 …__IO uint16_t PGPDO4; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
551 …__IO uint16_t PGPDO7; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
552 …__IO uint16_t PGPDO6; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
553 …__IO uint16_t PGPDO9; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
554 …__IO uint16_t PGPDO8; /**< SIUL2 Parallel GPIO Pad Data Out Register, o…
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/template/
DRTE_Device.h56 #define RTE_USART0_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Tx
59 #define RTE_USART0_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Rx
65 #define RTE_USART1_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Tx
68 #define RTE_USART1_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Rx
74 #define RTE_USART2_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Tx
77 #define RTE_USART2_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Rx
83 #define RTE_USART3_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Tx
86 #define RTE_USART3_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Rx
92 #define RTE_USART4_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Tx
95 #define RTE_USART4_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Rx
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/template/
DRTE_Device.h56 #define RTE_USART0_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Tx
59 #define RTE_USART0_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Rx
65 #define RTE_USART1_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Tx
68 #define RTE_USART1_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Rx
74 #define RTE_USART2_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Tx
77 #define RTE_USART2_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Rx
83 #define RTE_USART3_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Tx
86 #define RTE_USART3_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Rx
92 #define RTE_USART4_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Tx
95 #define RTE_USART4_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Rx
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/template/
DRTE_Device.h56 #define RTE_USART0_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Tx
59 #define RTE_USART0_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Rx
65 #define RTE_USART1_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Tx
68 #define RTE_USART1_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Rx
74 #define RTE_USART2_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Tx
77 #define RTE_USART2_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Rx
83 #define RTE_USART3_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Tx
86 #define RTE_USART3_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Rx
92 #define RTE_USART4_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Tx
95 #define RTE_USART4_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Rx
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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Include/dsp/
Dtransform_functions.h55 uint16_t fftLen; /**< length of the FFT. */
59 const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
60 …uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FF…
61 …uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with…
67 uint16_t fftLen,
82 uint16_t fftLen; /**< length of the FFT. */
86 const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
87 …uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FF…
88 …uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with…
94 uint16_t fftLen,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/pwm/
Dfsl_pwm.c67 static inline uint16_t PWM_GetComplementU16(uint16_t value) in PWM_GetComplementU16()
72 static inline uint16_t dutyCycleToReloadValue(uint8_t dutyCyclePercent) in dutyCycleToReloadValue()
104 …WM_SetPeriodRegister(PWM_Type *base, pwm_submodule_t subModule, pwm_mode_t mode, uint16_t pulseCnt) in PWM_SetPeriodRegister()
106 uint16_t modulo = 0; in PWM_SetPeriodRegister()
172 uint16_t pulseCnt, in PWM_SetDutycycleRegister()
173 uint16_t pwmHighPulse) in PWM_SetDutycycleRegister()
175 uint16_t modulo = 0; in PWM_SetDutycycleRegister()
270 uint16_t reg; in PWM_Init()
302 …~(uint16_t)(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | PWM_CTRL… in PWM_Init()
321 base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); in PWM_Init()
[all …]
Dfsl_pwm.h366 …uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in comp…
584 …, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle);
613 uint16_t pulseCnt,
614 uint16_t dutyCycle);
737 uint16_t reg = base->SM[subModule].DMAEN; in PWM_DMAFIFOWatermarkControl()
740 reg &= ~((uint16_t)PWM_DMAEN_FAND_MASK); in PWM_DMAFIFOWatermarkControl()
744 reg |= ((uint16_t)PWM_DMAEN_FAND_MASK); in PWM_DMAFIFOWatermarkControl()
760 uint16_t reg = base->SM[subModule].DMAEN; in PWM_DMACaptureSourceSelect()
762 reg &= ~((uint16_t)PWM_DMAEN_CAPTDE_MASK); in PWM_DMACaptureSourceSelect()
763 …reg |= (((uint16_t)pwm_dma_source_select << (uint16_t)PWM_DMAEN_CAPTDE_SHIFT) & (uint16_t)PWM_DMAE… in PWM_DMACaptureSourceSelect()
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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Include/
Darm_common_tables.h43 extern const uint16_t armBitRevTable[1024];
263 #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
264 extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
268 #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
269 extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
273 #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
274 extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
278 #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
279 extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
283 #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h13862 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
13864 …__IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), …
13865 …__IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0)…
13867 …__IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 …
13869 …__I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an en…
13871 …__IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls,…
13872 …__I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offse…
13874 …__IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: …
13876 …__IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: …
13878 …__IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: …
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h13860 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
13862 …__IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), …
13863 …__IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0)…
13865 …__IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 …
13867 …__I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an en…
13869 …__IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls,…
13870 …__I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offse…
13872 …__IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: …
13874 …__IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: …
13876 …__IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: …
[all …]

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