| /hal_nxp-latest/mcux/mcux-sdk/drivers/llwu/ |
| D | fsl_llwu.h | 118 uint32_t u32; in LLWU_GetVersionId() member
121 llwuVID.u32 = base->VERID; in LLWU_GetVersionId()
142 uint32_t u32; in LLWU_GetParam() member
145 llwuParam.u32 = base->PARAM; in LLWU_GetParam()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/spdif/ |
| D | fsl_spdif_edma.c | 39 uint32_t u32; member
479 destAddr.u32 = SPDIF_TxGetLeftDataRegisterAddress(base); in SPDIF_TransferSendEDMA()
512 destAddr.u32 = SPDIF_TxGetRightDataRegisterAddress(base); in SPDIF_TransferSendEDMA()
549 srcAddr.u32 = SPDIF_RxGetLeftDataRegisterAddress(base); in SPDIF_TransferReceiveEDMA()
583 srcAddr.u32 = SPDIF_RxGetRightDataRegisterAddress(base); in SPDIF_TransferReceiveEDMA()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/pxp/ |
| D | fsl_pxp.c | 82 uint32_t u32; member
88 uint32_t u32; member
203 uint32_t floatBits = u32_f32.u32; in PXP_ConvertFloat()
758 base->NEXT = PXP_ADDR_CPU_2_IP(addr.u32) & PXP_NEXT_POINTER_MASK; in PXP_SetNextCommand()
1029 uint32_t u32; in PXP_SetPorterDuffConfig() member
1037 base->ALPHA_A_CTRL = pdConfig.u32; in PXP_SetPorterDuffConfig()
1041 base->ALPHA_B_CTRL = pdConfig.u32; in PXP_SetPorterDuffConfig()
1066 uint32_t u32; in PXP_SetPorterDuffConfig() member
1071 base->PORTER_DUFF_CTRL = pdConfig.u32; in PXP_SetPorterDuffConfig()
1114 uint32_t u32; in PXP_GetPorterDuffConfigExt() member
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/ |
| D | fsl_clock.h | 797 uint32_t u32; in CLOCK_SetRunModeSysClkConfig() member
801 CLOCK_REG(&SCG0->RCCR) = scgSysClkConfig.u32; in CLOCK_SetRunModeSysClkConfig()
818 uint32_t u32; in CLOCK_GetCurSysClkConfig() member
821 scgSysClkConfig.u32 = CLOCK_REG(&SCG0->CSR); in CLOCK_GetCurSysClkConfig()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/ |
| D | fsl_clock.h | 797 uint32_t u32; in CLOCK_SetRunModeSysClkConfig() member
801 CLOCK_REG(&SCG0->RCCR) = scgSysClkConfig.u32; in CLOCK_SetRunModeSysClkConfig()
818 uint32_t u32; in CLOCK_GetCurSysClkConfig() member
821 scgSysClkConfig.u32 = CLOCK_REG(&SCG0->CSR); in CLOCK_GetCurSysClkConfig()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/ |
| D | fsl_clock.h | 859 uint32_t u32; in CLOCK_SetRunModeSysClkConfig() member
863 CLOCK_REG(&SCG0->RCCR) = scgSysClkConfig.u32; in CLOCK_SetRunModeSysClkConfig()
880 uint32_t u32; in CLOCK_GetCurSysClkConfig() member
883 scgSysClkConfig.u32 = CLOCK_REG(&SCG0->CSR); in CLOCK_GetCurSysClkConfig()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/ |
| D | fsl_qspi_edma.c | 40 uint32_t u32; member
220 destAddr.u32 = QSPI_GetTxDataRegisterAddress(base); in QSPI_TransferSendEDMA()
273 srcAddr.u32 = QSPI_GetRxDataRegisterAddress(base); in QSPI_TransferReceiveEDMA()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| D | rpc.h | 66 #define RPC_U32(MESG, IDX) ((MESG)->DATA.u32[(IDX) / 4U])
143 uint32_t u32[(SC_RPC_MAX_MSG - 1U)]; member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| D | rpc.h | 66 #define RPC_U32(MESG, IDX) ((MESG)->DATA.u32[(IDX) / 4U])
143 uint32_t u32[(SC_RPC_MAX_MSG - 1U)]; member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/scfw_api/main/ |
| D | ipc_imx8qm.c | 120 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
160 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/scfw_api/main/ |
| D | ipc_imx8qx.c | 116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT]; in sc_ipc_read()
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U]; in sc_ipc_write()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/pmc/ |
| D | fsl_pmc.h | 185 uint32_t u32; in PMC_GetVersionId() member
188 pmcVID.u32 = base->VERID; in PMC_GetVersionId()
|
