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Searched refs:timing (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/semc/
Dfsl_semc.c436 uint32_t timing; in SEMC_ConfigureSDRAM() local
497 timing = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
498 timing |= SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
499 timing |= SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
500 timing |= SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
501 timing |= SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
502 timing |= SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
504 base->SDRAMCR1 = timing; in SEMC_ConfigureSDRAM()
506 timing = SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
507 timing |= SEMC_SDRAMCR2_REF2REF(SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)); in SEMC_ConfigureSDRAM()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/emc/
Dfsl_emc.c230 emc_dynamic_timing_config_t *timing, in EMC_DynamicMemInit() argument
235 assert(NULL != timing); in EMC_DynamicMemInit()
266 base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig); in EMC_DynamicMemInit()
267 …base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MA… in EMC_DynamicMemInit()
268 …base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS… in EMC_DynamicMemInit()
269 …base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TS… in EMC_DynamicMemInit()
270 …base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR… in EMC_DynamicMemInit()
271 …base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL… in EMC_DynamicMemInit()
272 …base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MA… in EMC_DynamicMemInit()
273 …base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MA… in EMC_DynamicMemInit()
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Dfsl_emc.h212 emc_dynamic_timing_config_t *timing,
/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93qsb/
Dboard.c547 void BOARD_DRAM_PHY_Restore(struct dram_timing_info *timing) in BOARD_DRAM_PHY_Restore() argument
549 struct dram_cfg_param *cfg = timing->ddrphy_cfg; in BOARD_DRAM_PHY_Restore()
553 cfg = timing->ddrphy_cfg; in BOARD_DRAM_PHY_Restore()
554 for (i = 0U; i < timing->ddrphy_cfg_num; i++) in BOARD_DRAM_PHY_Restore()
564 cfg = timing->ddrphy_trained_csr; in BOARD_DRAM_PHY_Restore()
565 for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) in BOARD_DRAM_PHY_Restore()
575 cfg = timing->ddrphy_pie; in BOARD_DRAM_PHY_Restore()
576 for (i = 0U; i < timing->ddrphy_pie_num; i++) in BOARD_DRAM_PHY_Restore()
583 void BOARD_DDRC_Restore(struct dram_timing_info *timing) in BOARD_DDRC_Restore() argument
585 struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; in BOARD_DDRC_Restore()
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/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93evk/
Dboard.c589 void BOARD_DRAM_PHY_Restore(struct dram_timing_info *timing) in BOARD_DRAM_PHY_Restore() argument
591 struct dram_cfg_param *cfg = timing->ddrphy_cfg; in BOARD_DRAM_PHY_Restore()
595 cfg = timing->ddrphy_cfg; in BOARD_DRAM_PHY_Restore()
596 for (i = 0U; i < timing->ddrphy_cfg_num; i++) in BOARD_DRAM_PHY_Restore()
606 cfg = timing->ddrphy_trained_csr; in BOARD_DRAM_PHY_Restore()
607 for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) in BOARD_DRAM_PHY_Restore()
617 cfg = timing->ddrphy_pie; in BOARD_DRAM_PHY_Restore()
618 for (i = 0U; i < timing->ddrphy_pie_num; i++) in BOARD_DRAM_PHY_Restore()
625 void BOARD_DDRC_Restore(struct dram_timing_info *timing) in BOARD_DDRC_Restore() argument
627 struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; in BOARD_DDRC_Restore()
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/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93autoevk/
Dboard.c560 void BOARD_DRAM_PHY_Restore(struct dram_timing_info *timing) in BOARD_DRAM_PHY_Restore() argument
562 struct dram_cfg_param *cfg = timing->ddrphy_cfg; in BOARD_DRAM_PHY_Restore()
566 cfg = timing->ddrphy_cfg; in BOARD_DRAM_PHY_Restore()
567 for (i = 0U; i < timing->ddrphy_cfg_num; i++) in BOARD_DRAM_PHY_Restore()
577 cfg = timing->ddrphy_trained_csr; in BOARD_DRAM_PHY_Restore()
578 for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) in BOARD_DRAM_PHY_Restore()
588 cfg = timing->ddrphy_pie; in BOARD_DRAM_PHY_Restore()
589 for (i = 0U; i < timing->ddrphy_pie_num; i++) in BOARD_DRAM_PHY_Restore()
596 void BOARD_DDRC_Restore(struct dram_timing_info *timing) in BOARD_DDRC_Restore() argument
598 struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; in BOARD_DDRC_Restore()
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/hal_nxp-latest/imx/drivers/
Dflexcan.c121 FLEXCAN_SetTiming(base, &initConfig->timing); in FLEXCAN_Init()
229 void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing) in FLEXCAN_SetTiming() argument
231 assert(timing); in FLEXCAN_SetTiming()
242 CAN_CTRL1_REG(base) |= (CAN_CTRL1_PRESDIV(timing->preDiv) | \ in FLEXCAN_SetTiming()
243 CAN_CTRL1_RJW(timing->rJumpwidth) | \ in FLEXCAN_SetTiming()
244 CAN_CTRL1_PSEG1(timing->phaseSeg1) | \ in FLEXCAN_SetTiming()
245 CAN_CTRL1_PSEG2(timing->phaseSeg2) | \ in FLEXCAN_SetTiming()
246 CAN_CTRL1_PROP_SEG(timing->propSeg)); in FLEXCAN_SetTiming()
Dflexcan.h247 flexcan_timing_t timing; /*!< Desired FlexCAN module timing configuration. */ member
300 void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing);
/hal_nxp-latest/mcux/middleware/wifi_nxp/
DREADME.txt47 * FTM fine timing measurement\n
81 * TSF timing synchronization function\n
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/
DREADME.md43 …/or find the lowest-power state achievable depending on user constraints or timing (if declared):
44 …timing do not match the constraints of the low-power state, the SDK Power Manager will find a ligh…