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Searched refs:temp32 (Results 1 – 25 of 43) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_pmu.c195 uint32_t temp32; in PMU_StaticEnablePllLdo() local
197 temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); in PMU_StaticEnablePllLdo()
199 if (temp32 != in PMU_StaticEnablePllLdo()
443 uint32_t temp32 = base->PMU_LDO_LPSR_DIG; in PMU_StaticLpsrDigLdoInit() local
445 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticLpsrDigLdoInit()
446 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticLpsrDigLdoInit()
447 base->PMU_LDO_LPSR_DIG = temp32; in PMU_StaticLpsrDigLdoInit()
449 temp32 = base->PMU_LDO_LPSR_DIG_2; in PMU_StaticLpsrDigLdoInit()
450 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; in PMU_StaticLpsrDigLdoInit()
451 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); in PMU_StaticLpsrDigLdoInit()
[all …]
Dfsl_pgmc.c189 uint32_t temp32; in PGMC_CPC_CACHE_ControlByCpuPowerMode() local
192 temp32 = base->CPC_CACHE_CM_CTRL; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
196 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
197 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
200 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
201 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
204 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
205 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
208 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
209 …base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
[all …]
Dfsl_gpc.c269 uint32_t temp32; in GPC_CM_ClearInterruptStatusFlags() local
271 temp32 = base->CM_INT_CTRL; in GPC_CM_ClearInterruptStatusFlags()
272 temp32 &= ~(GPC_CM_ALL_INTERRUPT_STATUS); in GPC_CM_ClearInterruptStatusFlags()
273 base->CM_INT_CTRL = (mask | temp32); in GPC_CM_ClearInterruptStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_pmu.c195 uint32_t temp32; in PMU_StaticEnablePllLdo() local
197 temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); in PMU_StaticEnablePllLdo()
199 if (temp32 != in PMU_StaticEnablePllLdo()
443 uint32_t temp32 = base->PMU_LDO_LPSR_DIG; in PMU_StaticLpsrDigLdoInit() local
445 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticLpsrDigLdoInit()
446 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticLpsrDigLdoInit()
447 base->PMU_LDO_LPSR_DIG = temp32; in PMU_StaticLpsrDigLdoInit()
449 temp32 = base->PMU_LDO_LPSR_DIG_2; in PMU_StaticLpsrDigLdoInit()
450 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; in PMU_StaticLpsrDigLdoInit()
451 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); in PMU_StaticLpsrDigLdoInit()
[all …]
Dfsl_pgmc.c189 uint32_t temp32; in PGMC_CPC_CACHE_ControlByCpuPowerMode() local
192 temp32 = base->CPC_CACHE_CM_CTRL; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
196 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
197 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
200 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
201 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
204 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
205 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
208 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
209 …base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
[all …]
Dfsl_gpc.c269 uint32_t temp32; in GPC_CM_ClearInterruptStatusFlags() local
271 temp32 = base->CM_INT_CTRL; in GPC_CM_ClearInterruptStatusFlags()
272 temp32 &= ~(GPC_CM_ALL_INTERRUPT_STATUS); in GPC_CM_ClearInterruptStatusFlags()
273 base->CM_INT_CTRL = (mask | temp32); in GPC_CM_ClearInterruptStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_pmu.c195 uint32_t temp32; in PMU_StaticEnablePllLdo() local
197 temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); in PMU_StaticEnablePllLdo()
199 if (temp32 != in PMU_StaticEnablePllLdo()
443 uint32_t temp32 = base->PMU_LDO_LPSR_DIG; in PMU_StaticLpsrDigLdoInit() local
445 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticLpsrDigLdoInit()
446 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticLpsrDigLdoInit()
447 base->PMU_LDO_LPSR_DIG = temp32; in PMU_StaticLpsrDigLdoInit()
449 temp32 = base->PMU_LDO_LPSR_DIG_2; in PMU_StaticLpsrDigLdoInit()
450 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; in PMU_StaticLpsrDigLdoInit()
451 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); in PMU_StaticLpsrDigLdoInit()
[all …]
Dfsl_pgmc.c189 uint32_t temp32; in PGMC_CPC_CACHE_ControlByCpuPowerMode() local
192 temp32 = base->CPC_CACHE_CM_CTRL; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
196 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
197 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
200 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
201 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
204 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
205 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
208 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
209 …base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
[all …]
Dfsl_gpc.c269 uint32_t temp32; in GPC_CM_ClearInterruptStatusFlags() local
271 temp32 = base->CM_INT_CTRL; in GPC_CM_ClearInterruptStatusFlags()
272 temp32 &= ~(GPC_CM_ALL_INTERRUPT_STATUS); in GPC_CM_ClearInterruptStatusFlags()
273 base->CM_INT_CTRL = (mask | temp32); in GPC_CM_ClearInterruptStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_pmu.c195 uint32_t temp32; in PMU_StaticEnablePllLdo() local
197 temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); in PMU_StaticEnablePllLdo()
199 if (temp32 != in PMU_StaticEnablePllLdo()
443 uint32_t temp32 = base->PMU_LDO_LPSR_DIG; in PMU_StaticLpsrDigLdoInit() local
445 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticLpsrDigLdoInit()
446 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticLpsrDigLdoInit()
447 base->PMU_LDO_LPSR_DIG = temp32; in PMU_StaticLpsrDigLdoInit()
449 temp32 = base->PMU_LDO_LPSR_DIG_2; in PMU_StaticLpsrDigLdoInit()
450 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; in PMU_StaticLpsrDigLdoInit()
451 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); in PMU_StaticLpsrDigLdoInit()
[all …]
Dfsl_pgmc.c189 uint32_t temp32; in PGMC_CPC_CACHE_ControlByCpuPowerMode() local
192 temp32 = base->CPC_CACHE_CM_CTRL; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
196 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
197 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
200 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
201 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
204 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
205 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
208 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
209 …base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_pmu.c195 uint32_t temp32; in PMU_StaticEnablePllLdo() local
197 temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); in PMU_StaticEnablePllLdo()
199 if (temp32 != in PMU_StaticEnablePllLdo()
443 uint32_t temp32 = base->PMU_LDO_LPSR_DIG; in PMU_StaticLpsrDigLdoInit() local
445 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticLpsrDigLdoInit()
446 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticLpsrDigLdoInit()
447 base->PMU_LDO_LPSR_DIG = temp32; in PMU_StaticLpsrDigLdoInit()
449 temp32 = base->PMU_LDO_LPSR_DIG_2; in PMU_StaticLpsrDigLdoInit()
450 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; in PMU_StaticLpsrDigLdoInit()
451 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); in PMU_StaticLpsrDigLdoInit()
[all …]
Dfsl_pgmc.c189 uint32_t temp32; in PGMC_CPC_CACHE_ControlByCpuPowerMode() local
192 temp32 = base->CPC_CACHE_CM_CTRL; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
196 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
197 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
200 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
201 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
204 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
205 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
208 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
209 …base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_pmu.c195 uint32_t temp32; in PMU_StaticEnablePllLdo() local
197 temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); in PMU_StaticEnablePllLdo()
199 if (temp32 != in PMU_StaticEnablePllLdo()
443 uint32_t temp32 = base->PMU_LDO_LPSR_DIG; in PMU_StaticLpsrDigLdoInit() local
445 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticLpsrDigLdoInit()
446 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticLpsrDigLdoInit()
447 base->PMU_LDO_LPSR_DIG = temp32; in PMU_StaticLpsrDigLdoInit()
449 temp32 = base->PMU_LDO_LPSR_DIG_2; in PMU_StaticLpsrDigLdoInit()
450 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; in PMU_StaticLpsrDigLdoInit()
451 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); in PMU_StaticLpsrDigLdoInit()
[all …]
Dfsl_pgmc.c189 uint32_t temp32; in PGMC_CPC_CACHE_ControlByCpuPowerMode() local
192 temp32 = base->CPC_CACHE_CM_CTRL; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
196 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
197 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
200 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
201 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
204 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
205 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
208 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
209 …base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_pmu.c195 uint32_t temp32; in PMU_StaticEnablePllLdo() local
197 temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); in PMU_StaticEnablePllLdo()
199 if (temp32 != in PMU_StaticEnablePllLdo()
443 uint32_t temp32 = base->PMU_LDO_LPSR_DIG; in PMU_StaticLpsrDigLdoInit() local
445 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticLpsrDigLdoInit()
446 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticLpsrDigLdoInit()
447 base->PMU_LDO_LPSR_DIG = temp32; in PMU_StaticLpsrDigLdoInit()
449 temp32 = base->PMU_LDO_LPSR_DIG_2; in PMU_StaticLpsrDigLdoInit()
450 temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; in PMU_StaticLpsrDigLdoInit()
451 temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); in PMU_StaticLpsrDigLdoInit()
[all …]
Dfsl_pgmc.c189 uint32_t temp32; in PGMC_CPC_CACHE_ControlByCpuPowerMode() local
192 temp32 = base->CPC_CACHE_CM_CTRL; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
196 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
197 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
200 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
201 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
204 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
205 … base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
208 temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; in PGMC_CPC_CACHE_ControlByCpuPowerMode()
209 …base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); in PGMC_CPC_CACHE_ControlByCpuPowerMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/puf/
Dfsl_puf.c298 register uint32_t temp32 = 0; in PUF_Enroll() local
333 temp32 = base->CODEOUTPUT; in PUF_Enroll()
336 *activationCodeAligned = temp32; in PUF_Enroll()
367 register uint32_t temp32 = 0; in PUF_Start() local
404 temp32 = *activationCodeAligned; in PUF_Start()
408 base->CODEINPUT = temp32; in PUF_Start()
443 register uint32_t temp32 = 0; in PUF_SetIntrinsicKey() local
493 temp32 = base->CODEOUTPUT; in PUF_SetIntrinsicKey()
496 *keyCodeAligned = temp32; in PUF_SetIntrinsicKey()
538 register uint32_t temp32 = 0; in PUF_SetUserKey() local
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_pmu.c83 uint32_t temp32; in PMU_StaticEnablePllLdo() local
85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
87 if (temp32 != in PMU_StaticEnablePllLdo()
209 uint32_t temp32 = base->PMU_LDO_AON_DIG; in PMU_StaticAonDigLdoInit() local
211 temp32 &= ~ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticAonDigLdoInit()
212 temp32 |= ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticAonDigLdoInit()
213 base->PMU_LDO_AON_DIG = temp32; in PMU_StaticAonDigLdoInit()
348 uint32_t temp32; in PMU_StaticBandgapInit() local
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
351 temp32 &= ~(VMBANDGAP_CTRL0_REFTOP_PWD_MASK | VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | in PMU_StaticBandgapInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_pmu.c83 uint32_t temp32; in PMU_StaticEnablePllLdo() local
85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
87 if (temp32 != in PMU_StaticEnablePllLdo()
209 uint32_t temp32 = base->PMU_LDO_AON_DIG; in PMU_StaticAonDigLdoInit() local
211 temp32 &= ~ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticAonDigLdoInit()
212 temp32 |= ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticAonDigLdoInit()
213 base->PMU_LDO_AON_DIG = temp32; in PMU_StaticAonDigLdoInit()
348 uint32_t temp32; in PMU_StaticBandgapInit() local
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
351 temp32 &= ~(VMBANDGAP_CTRL0_REFTOP_PWD_MASK | VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | in PMU_StaticBandgapInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_pmu.c83 uint32_t temp32; in PMU_StaticEnablePllLdo() local
85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
87 if (temp32 != in PMU_StaticEnablePllLdo()
209 uint32_t temp32 = base->PMU_LDO_AON_DIG; in PMU_StaticAonDigLdoInit() local
211 temp32 &= ~ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticAonDigLdoInit()
212 temp32 |= ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticAonDigLdoInit()
213 base->PMU_LDO_AON_DIG = temp32; in PMU_StaticAonDigLdoInit()
348 uint32_t temp32; in PMU_StaticBandgapInit() local
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
351 temp32 &= ~(VMBANDGAP_CTRL0_REFTOP_PWD_MASK | VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | in PMU_StaticBandgapInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_pmu.c83 uint32_t temp32; in PMU_StaticEnablePllLdo() local
85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
87 if (temp32 != in PMU_StaticEnablePllLdo()
209 uint32_t temp32 = base->PMU_LDO_AON_DIG; in PMU_StaticAonDigLdoInit() local
211 temp32 &= ~ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_MASK; in PMU_StaticAonDigLdoInit()
212 temp32 |= ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT(config->targetVoltage); in PMU_StaticAonDigLdoInit()
213 base->PMU_LDO_AON_DIG = temp32; in PMU_StaticAonDigLdoInit()
348 uint32_t temp32; in PMU_StaticBandgapInit() local
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
351 temp32 &= ~(VMBANDGAP_CTRL0_REFTOP_PWD_MASK | VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | in PMU_StaticBandgapInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/spm/
Dfsl_spm.c189 uint32_t temp32; in SPM_SetDcdcLoopControlConfig() local
191 temp32 = base->DCDCC1; in SPM_SetDcdcLoopControlConfig()
192 … temp32 &= ~(SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK | SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK); in SPM_SetDcdcLoopControlConfig()
193 temp32 |= SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST(config->enableCommonHysteresis) | in SPM_SetDcdcLoopControlConfig()
195 base->DCDCC1 = temp32; in SPM_SetDcdcLoopControlConfig()
197 temp32 = base->DCDCC2; in SPM_SetDcdcLoopControlConfig()
198 temp32 &= ~SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK; in SPM_SetDcdcLoopControlConfig()
199 temp32 |= SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN(config->invertHysteresisSign); in SPM_SetDcdcLoopControlConfig()
200 base->DCDCC2 = temp32; in SPM_SetDcdcLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/ssarc/
Dfsl_ssarc.c106 uint32_t temp32 = 0UL; in SSARC_SetDescriptorConfig() local
111 temp32 = SSARC_HP_SRAM2_TYPE(config->type) | SSARC_HP_SRAM2_SIZE(config->size); in SSARC_SetDescriptorConfig()
112 temp32 |= (uint32_t)(config->operation); in SSARC_SetDescriptorConfig()
114 base->DESC[index].SRAM2 = temp32; in SSARC_SetDescriptorConfig()
141 uint32_t temp32; in SSARC_GroupInit() local
143 temp32 = SSARC_LP_DESC_CTRL1_POWER_DOMAIN(config->powerDomain) | in SSARC_GroupInit()
146 base->GROUPS[groupID].DESC_CTRL1 = temp32; in SSARC_GroupInit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/puf_v3/
Dfsl_puf_v3.c230 register uint32_t temp32 = 0; in PUF_Enroll() local
265 temp32 = base->DOR; in PUF_Enroll()
268 *activationCodeAligned = temp32; in PUF_Enroll()
305 register uint32_t temp32 = 0; in PUF_Start() local
345 temp32 = *activationCodeAligned; in PUF_Start()
353 temp32 = *activationCodeAligned; in PUF_Start()
357 base->DIR = temp32; in PUF_Start()

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