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Searched refs:step (Results 1 – 25 of 65) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_gpc.c91 gpc_cm_tran_step_t step, in GPC_CM_ConfigCpuModeTransitionStep() argument
94 if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) in GPC_CM_ConfigCpuModeTransitionStep()
96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
284 gpc_sp_tran_step_t step, in GPC_SP_ConfigSetPointTransitionStep() argument
287 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); in GPC_SP_ConfigSetPointTransitionStep()
304 *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; in GPC_SP_ConfigSetPointTransitionStep()
315 gpc_stby_tran_step_t step, in GPC_STBY_ConfigStandbyTransitionStep() argument
318 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); in GPC_STBY_ConfigStandbyTransitionStep()
334 *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; in GPC_STBY_ConfigStandbyTransitionStep()
Dfsl_gpc.h438 gpc_cm_tran_step_t step,
590 gpc_sp_tran_step_t step,
645 gpc_stby_tran_step_t step,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_gpc.c117 void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable) in GPC_CM_EnableCpuModeTransitionStep() argument
119 if (!((step >= kGPC_CM_SleepSYS) && (step <= kGPC_CM_WakeupSYS))) in GPC_CM_EnableCpuModeTransitionStep()
121 … uint32_t tmp32 = *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]); in GPC_CM_EnableCpuModeTransitionStep()
131 *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]) = tmp32; in GPC_CM_EnableCpuModeTransitionStep()
198 void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step,… in GPC_SS_EnableSystemSleepTransitionStep() argument
200 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]); in GPC_SS_EnableSystemSleepTransitionStep()
210 *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]) = tmp32; in GPC_SS_EnableSystemSleepTransitionStep()
Dfsl_soc_src.c77 void SRC_SLICE_SoftwareControl(SRC_MIX_SLICE_Type *base, src_power_ctrl_step_t step) in SRC_SLICE_SoftwareControl() argument
81 switch (step) in SRC_SLICE_SoftwareControl()
Dfsl_gpc.h329 void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable…
377 void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step,…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_gpc.c117 void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable) in GPC_CM_EnableCpuModeTransitionStep() argument
119 if (!((step >= kGPC_CM_SleepSYS) && (step <= kGPC_CM_WakeupSYS))) in GPC_CM_EnableCpuModeTransitionStep()
121 … uint32_t tmp32 = *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]); in GPC_CM_EnableCpuModeTransitionStep()
131 *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]) = tmp32; in GPC_CM_EnableCpuModeTransitionStep()
198 void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step,… in GPC_SS_EnableSystemSleepTransitionStep() argument
200 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]); in GPC_SS_EnableSystemSleepTransitionStep()
210 *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]) = tmp32; in GPC_SS_EnableSystemSleepTransitionStep()
Dfsl_soc_src.c77 void SRC_SLICE_SoftwareControl(SRC_MIX_SLICE_Type *base, src_power_ctrl_step_t step) in SRC_SLICE_SoftwareControl() argument
81 switch (step) in SRC_SLICE_SoftwareControl()
Dfsl_gpc.h329 void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable…
377 void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step,…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_gpc.c117 void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable) in GPC_CM_EnableCpuModeTransitionStep() argument
119 if (!((step >= kGPC_CM_SleepSYS) && (step <= kGPC_CM_WakeupSYS))) in GPC_CM_EnableCpuModeTransitionStep()
121 … uint32_t tmp32 = *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]); in GPC_CM_EnableCpuModeTransitionStep()
131 *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]) = tmp32; in GPC_CM_EnableCpuModeTransitionStep()
198 void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step,… in GPC_SS_EnableSystemSleepTransitionStep() argument
200 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]); in GPC_SS_EnableSystemSleepTransitionStep()
210 *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]) = tmp32; in GPC_SS_EnableSystemSleepTransitionStep()
Dfsl_soc_src.c77 void SRC_SLICE_SoftwareControl(SRC_MIX_SLICE_Type *base, src_power_ctrl_step_t step) in SRC_SLICE_SoftwareControl() argument
81 switch (step) in SRC_SLICE_SoftwareControl()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_gpc.c117 void GPC_CM_EnableCpuModeTransitionStep(gpc_cpu_slice_t slice, gpc_cm_tran_step_t step, bool enable) in GPC_CM_EnableCpuModeTransitionStep() argument
119 if (!((step >= kGPC_CM_SleepSYS) && (step <= kGPC_CM_WakeupSYS))) in GPC_CM_EnableCpuModeTransitionStep()
121 … uint32_t tmp32 = *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]); in GPC_CM_EnableCpuModeTransitionStep()
131 *(uint32_t *)((uint32_t)(&GPC_CPU_CTRL->AUTHEN[slice]) + s_cmRegOffset[step]) = tmp32; in GPC_CM_EnableCpuModeTransitionStep()
198 void GPC_SS_EnableSystemSleepTransitionStep(GPC_SYS_SLEEP_CTRL_Type *base, gpc_ss_tran_step_t step,… in GPC_SS_EnableSystemSleepTransitionStep() argument
200 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]); in GPC_SS_EnableSystemSleepTransitionStep()
210 *(uint32_t *)((uint32_t)base + s_ssRegOffset[step]) = tmp32; in GPC_SS_EnableSystemSleepTransitionStep()
Dfsl_soc_src.c77 void SRC_SLICE_SoftwareControl(SRC_MIX_SLICE_Type *base, src_power_ctrl_step_t step) in SRC_SLICE_SoftwareControl() argument
81 switch (step) in SRC_SLICE_SoftwareControl()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/SupportFunctions/
Darm_bitonic_sort_f32.c37 uint32_t step; in arm_bitonic_sort_core_f32() local
42 step = n>>1; in arm_bitonic_sort_core_f32()
46 for(k=0; k<step; k++) in arm_bitonic_sort_core_f32()
61 for(step=(n>>2); step>0; step/=2) in arm_bitonic_sort_core_f32()
63 for(j=0; j<n; j=j+step*2) in arm_bitonic_sort_core_f32()
66 rightPtr = pSrc+j+step; in arm_bitonic_sort_core_f32()
68 for(k=0; k<step; k++) in arm_bitonic_sort_core_f32()

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