1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_MSMC_H_
9 #define FSL_MSMC_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup msmc */
14 /*! @{*/
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief MSMC driver version. */
25 #define FSL_MSMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
26 /*! @} */
27
28 /*!
29 * @brief Power Modes Protection
30 */
31 typedef enum _smc_power_mode_protection
32 {
33 kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */
34 kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */
35 kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */
36 kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */
37 kSMC_AllowPowerModeAll = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK |
38 SMC_PMPROT_AHSRUN_MASK /*!< Allow all power mode. */
39 } smc_power_mode_protection_t;
40
41 /*!
42 * @brief Power Modes in PMSTAT
43 */
44 typedef enum _smc_power_state
45 {
46 kSMC_PowerStateRun = 1U, /*!< 0000_0001 - Current power mode is RUN */
47 kSMC_PowerStateStop = 1U << 1U, /*!< 0000_0010 - Current power mode is any STOP mode */
48 kSMC_PowerStateVlpr = 1U << 2U, /*!< 0000_0100 - Current power mode is VLPR */
49 kSMC_PowerStateHsrun = 1U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
50 } smc_power_state_t;
51
52 /*!
53 * @brief Power Stop Entry Status in PMSTAT
54 */
55 typedef enum _smc_power_stop_entry_status
56 {
57 kSMC_PowerStopEntryAlt0 = 1U, /*!< Indicates a Stop mode entry since this field was last cleared. */
58 kSMC_PowerStopEntryAlt1 = 1U << 1, /*!< Indicates the system bus masters acknowledged the Stop mode entry. */
59 kSMC_PowerStopEntryAlt2 = 1U << 2, /*!< Indicates the system clock peripherals acknowledged the Stop mode entry. */
60 kSMC_PowerStopEntryAlt3 = 1U << 3, /*!< Indicates the bus clock peripherals acknowledged the Stop mode entry. */
61 kSMC_PowerStopEntryAlt4 = 1U << 4, /*!< Indicates the slow clock peripherals acknowledged the Stop mode entry. */
62 kSMC_PowerStopEntryAlt5 = 1U << 5, /*!< Indicates Stop mode entry completed. */
63 } smc_power_stop_entry_status_t;
64
65 /*!
66 * @brief Run mode definition
67 */
68 typedef enum _smc_run_mode
69 {
70 kSMC_RunNormal = 0U, /*!< normal RUN mode. */
71 kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */
72 kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */
73 } smc_run_mode_t;
74
75 /*!
76 * @brief Stop mode definition
77 */
78 typedef enum _smc_stop_mode
79 {
80 kSMC_StopNormal = 0U, /*!< Normal STOP mode. */
81 kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */
82 kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */
83 #if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
84 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
85 kSMC_StopVlls2 = 4U, /*!< Very-Low-Leakage Stop mode, VLPS2/3. */
86 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
87 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
88 kSMC_StopVlls0 = 6U, /*!< Very-Low-Leakage Stop mode, VLPS0/1. */
89 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
90 #else
91 kSMC_StopVlls = 4U, /*!< Very-Low-Leakage Stop mode. */
92 #endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
93 } smc_stop_mode_t;
94
95 /*!
96 * @brief Partial STOP option
97 */
98 typedef enum _smc_partial_stop_mode
99 {
100 kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/
101 kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
102 kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
103 kSMC_PartialStop3 = 3U, /*!< Partial Stop with system clock enabled and bus clock disabled*/
104 } smc_partial_stop_option_t;
105
106 /*!
107 * @brief SMC configuration status
108 */
109 enum
110 {
111 kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Entering Stop mode is abort*/
112 };
113
114 /*!
115 * @brief System Reset Source Name definitions
116 */
117 typedef enum _smc_reset_source
118 {
119 kSMC_SourceWakeup = SMC_SRS_WAKEUP_MASK, /*!< Very low-leakage wakeup reset */
120 kSMC_SourcePor = SMC_SRS_POR_MASK, /*!< Power on reset */
121 kSMC_SourceLvd = SMC_SRS_LVD_MASK, /*!< Low-voltage detect reset */
122 kSMC_SourceHvd = SMC_SRS_HVD_MASK, /*!< High-voltage detect reset */
123 kSMC_SourceWarm = SMC_SRS_WARM_MASK, /*!< Warm reset. Warm Reset flag will assert if any of the system reset
124 sources in this register assert (SRS[31:8]) */
125 kSMC_SourceFatal = SMC_SRS_FATAL_MASK, /*!< Fatal reset */
126 kSMC_SourceCore =
127 SMC_SRS_CORE_MASK, /*!< Software reset that only reset the core, NOT a sticky system reset source. */
128 kSMC_SourcePin = SMC_SRS_PIN_MASK, /*!< RESET_B pin reset. */
129 kSMC_SourceMdm = SMC_SRS_MDM_MASK, /*!< MDM reset. */
130 kSMC_SourceRstAck = SMC_SRS_RSTACK_MASK, /*!< Reset Controller timeout reset. */
131 kSMC_SourceStopAck = SMC_SRS_STOPACK_MASK, /*!< Stop timeout reset */
132 kSMC_SourceScg = SMC_SRS_SCG_MASK, /*!< SCG loss of lock or loss of clock */
133 kSMC_SourceWdog = SMC_SRS_WDOG_MASK, /*!< Watchdog reset */
134 kSMC_SourceSoftware = SMC_SRS_SW_MASK, /*!< Software reset */
135 kSMC_SourceLockup = SMC_SRS_LOCKUP_MASK, /*!< Lockup reset. Core lockup or exception. */
136 kSMC_SourceJtag = SMC_SRS_JTAG_MASK, /*!< JTAG system reset */
137 #if (defined(FSL_FEATURE_SMC_HAS_SRS_VBAT) && FSL_FEATURE_SMC_HAS_SRS_VBAT)
138 kSMC_SourceVbat = SMC_SRS_VBAT_MASK,
139 #endif
140 #if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
141 kSMC_SourceSecVio = SMC_SRS_SECVIO_MASK, /*!< Security violation reset */
142 #endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
143 #if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
144 kSMC_SourceTamper = SMC_SRS_TAMPER_MASK, /*!< Tamper reset */
145 #endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
146 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
147 kSMC_SourceCore0 = SMC_SRS_CORE0_MASK, /*!< Core0 System Reset. */
148 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
149 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
150 kSMC_SourceCore1 = SMC_SRS_CORE1_MASK, /*!< Core1 System Reset. */
151 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
152 /* Source All. */
153 kSMC_SourceAll = SMC_SRS_WAKEUP_MASK | SMC_SRS_POR_MASK | SMC_SRS_LVD_MASK | SMC_SRS_HVD_MASK | SMC_SRS_WARM_MASK |
154 SMC_SRS_FATAL_MASK | SMC_SRS_CORE_MASK | SMC_SRS_PIN_MASK | SMC_SRS_MDM_MASK |
155 SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK |
156 SMC_SRS_SW_MASK | SMC_SRS_LOCKUP_MASK | SMC_SRS_JTAG_MASK
157 #if (defined(FSL_FEATURE_SMC_HAS_SRS_VBAT) && FSL_FEATURE_SMC_HAS_SRS_VBAT)
158 | SMC_SRS_VBAT_MASK
159 #endif
160 #if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
161 | SMC_SRS_SECVIO_MASK
162 #endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
163 #if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
164 | SMC_SRS_TAMPER_MASK
165 #endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
166 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
167 | SMC_SRS_CORE0_MASK
168 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
169 #if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
170 | SMC_SRS_CORE1_MASK
171 #endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
172 ,
173 } smc_reset_source_t;
174
175 /*!
176 * @brief System reset interrupt enable bit definitions.
177 */
178 typedef enum _smc_interrupt_enable
179 {
180 kSMC_IntNone = 0U, /*!< No interrupt enabled. */
181 kSMC_IntPin = SMC_SRIE_PIN_MASK, /*!< Pin reset interrupt. */
182 kSMC_IntMdm = SMC_SRIE_MDM_MASK, /*!< MDM reset interrupt. */
183 kSMC_IntStopAck = SMC_SRIE_STOPACK_MASK, /*!< Stop timeout reset interrupt. */
184 kSMC_IntWdog = SMC_SRIE_WDOG_MASK, /*!< Watchdog interrupt. */
185 kSMC_IntSoftware = SMC_SRIE_SW_MASK, /*!< Software reset interrupts. */
186 kSMC_IntLockup = SMC_SRIE_LOCKUP_MASK, /*!< Lock up interrupt. */
187 #if defined(FSL_FEATURE_SMC_HAS_SRIE_VBAT) && FSL_FEATURE_SMC_HAS_SRIE_VBAT
188 kSMC_IntVbat = SMC_SRIE_VBAT_MASK,
189 #endif
190 #if (defined(FSL_FEATURE_SMC_HAS_SRIE_CORE0) && FSL_FEATURE_SMC_HAS_SRIE_CORE0)
191 kSMC_IntCore0 = SMC_SRIE_CORE0_MASK, /*! Core 0 interrupts. */
192 #endif /* FSL_FEATURE_SMC_HAS_SRIE_CORE0 */
193 #if (defined(FSL_FEATURE_SMC_HAS_SRIE_CORE1) && FSL_FEATURE_SMC_HAS_SRIE_CORE1)
194 kSMC_IntCore1 = SMC_SRIE_CORE1_MASK, /*! Core 1 interrupts. */
195 #endif /* FSL_FEATURE_SMC_HAS_SRIE_CORE1 */
196 kSMC_IntAll = SMC_SRIE_PIN_MASK | /*!< All system reset interrupts. */
197 SMC_SRIE_MDM_MASK | SMC_SRIE_STOPACK_MASK | SMC_SRIE_WDOG_MASK | SMC_SRIE_SW_MASK |
198 SMC_SRIE_LOCKUP_MASK
199 #if defined(FSL_FEATURE_SMC_HAS_SRIE_VBAT) && FSL_FEATURE_SMC_HAS_SRIE_VBAT
200 | SMC_SRIE_VBAT_MASK
201 #endif /* FSL_FEATURE_SMC_HAS_SRIE_VBAT */
202 #if (defined(FSL_FEATURE_SMC_HAS_SRIE_CORE0) && FSL_FEATURE_SMC_HAS_SRIE_CORE0)
203 | SMC_SRIE_CORE0_MASK
204 #endif /* FSL_FEATURE_SMC_HAS_SRIE_CORE0 */
205 #if (defined(FSL_FEATURE_SMC_HAS_SRIE_CORE1) && FSL_FEATURE_SMC_HAS_SRIE_CORE1)
206 | SMC_SRIE_CORE1_MASK
207 #endif /* FSL_FEATURE_SMC_HAS_SRIE_CORE1 */
208 } smc_interrupt_enable_t;
209
210 /*!
211 * @brief Reset pin filter configuration
212 */
213 typedef struct _smc_reset_pin_filter_config
214 {
215 uint8_t slowClockFilterCount; /*!< Reset pin bus clock filter width from 1 to 32 slow clock cycles. */
216 bool enableFilter; /*!< Reset pin filter enable/disable. */
217 #if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
218 bool enableLpoFilter; /*!< LPO clock reset pin filter enabled in all modes. */
219 #endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
220 } smc_reset_pin_filter_config_t;
221
222 /*******************************************************************************
223 * API
224 ******************************************************************************/
225 #if defined(__cplusplus)
226 extern "C" {
227 #endif /* __cplusplus*/
228
229 /*! @name System mode controller APIs*/
230 /*! @{ */
231
232 /*!
233 * @brief Configures all power mode protection settings.
234 *
235 * This function configures the power mode protection settings for
236 * supported power modes in the specified chip family. The available power modes
237 * are defined in the smc_power_mode_protection_t. This should be done at an early
238 * system level initialization stage. See the reference manual for details.
239 * This register can only write once after the power reset.
240 *
241 * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
242 * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeLls | kSMC_AllowPowerModeVlls).
243 * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
244 *
245 * @param base SMC peripheral base address.
246 * @param allowedModes Bitmap of the allowed power modes.
247 */
SMC_SetPowerModeProtection(SMC_Type * base,uint8_t allowedModes)248 static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
249 {
250 base->PMPROT = allowedModes;
251 }
252
253 /*!
254 * @brief Gets the current power mode status.
255 *
256 * This function returns the current power mode stat. Once application
257 * switches the power mode, it should always check the stat to check whether it
258 * runs into the specified mode or not. An application should check
259 * this mode before switching to a different mode. The system requires that
260 * only certain modes can switch to other specific modes. See the
261 * reference manual for details and the smc_power_state_t for information about
262 * the power stat.
263 *
264 * @param base SMC peripheral base address.
265 * @return Current power mode status.
266 */
SMC_GetPowerModeState(SMC_Type * base)267 static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
268 {
269 return (smc_power_state_t)(uint32_t)((base->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT);
270 }
271
272 #if (defined(FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) && FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT)
273 /*!
274 * @brief Gets the result of the previous stop mode entry.
275 *
276 * This function returns the result of the previous stop mode entry.
277 *
278 * @param base SMC peripheral base address.
279 * @return Current power stop entry status.
280 */
SMC_GetStopEntryStatus(SMC_Type * base)281 static inline smc_power_stop_entry_status_t SMC_GetStopEntryStatus(SMC_Type *base)
282 {
283 return (smc_power_stop_entry_status_t)(uint32_t)((base->PMSTAT & SMC_PMSTAT_STOPSTAT_MASK) >>
284 SMC_PMSTAT_STOPSTAT_SHIFT);
285 }
286
287 /*!
288 * @brief Clears all the result of the previous stop mode entry.
289 *
290 * This function clears all the result of the previous stop mode entry.
291 *
292 * @param base SMC peripheral base address.
293 * @return Current power stop entry status.
294 */
SMC_ClearStopEntryStatus(SMC_Type * base)295 static inline void SMC_ClearStopEntryStatus(SMC_Type *base)
296 {
297 /* Only write 0x01 to clear this field, all other writes are ignored. */
298 base->PMSTAT = (base->PMSTAT & ~SMC_PMSTAT_STOPSTAT_MASK) | SMC_PMSTAT_STOPSTAT(0x01);
299 }
300
301 #endif /* FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT */
302
303 /*!
304 * @brief Prepare to enter stop modes
305 *
306 * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
307 */
SMC_PreEnterStopModes(void)308 static inline void SMC_PreEnterStopModes(void)
309 {
310 __disable_irq();
311 __ISB();
312 }
313
314 /*!
315 * @brief Recovering after wake up from stop modes
316 *
317 * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
318 * It is used together with @ref SMC_PreEnterStopModes.
319 */
SMC_PostExitStopModes(void)320 static inline void SMC_PostExitStopModes(void)
321 {
322 __enable_irq();
323 __ISB();
324 }
325
326 /*!
327 * @brief Prepare to enter wait modes
328 *
329 * This function should be called before entering WAIT/VLPW modes..
330 */
SMC_PreEnterWaitModes(void)331 static inline void SMC_PreEnterWaitModes(void)
332 {
333 __disable_irq();
334 __ISB();
335 }
336
337 /*!
338 * @brief Recovering after wake up from stop modes
339 *
340 * This function should be called after wake up from WAIT/VLPW modes.
341 * It is used together with @ref SMC_PreEnterWaitModes.
342 */
SMC_PostExitWaitModes(void)343 static inline void SMC_PostExitWaitModes(void)
344 {
345 __enable_irq();
346 __ISB();
347 }
348
349 /*!
350 * @brief Configure the system to RUN power mode.
351 *
352 * @param base SMC peripheral base address.
353 * @return SMC configuration error code.
354 */
355 status_t SMC_SetPowerModeRun(SMC_Type *base);
356
357 /*!
358 * @brief Configure the system to HSRUN power mode.
359 *
360 * @param base SMC peripheral base address.
361 * @return SMC configuration error code.
362 */
363 status_t SMC_SetPowerModeHsrun(SMC_Type *base);
364
365 /*!
366 * @brief Configure the system to WAIT power mode.
367 *
368 * @param base SMC peripheral base address.
369 * @return SMC configuration error code.
370 */
371 status_t SMC_SetPowerModeWait(SMC_Type *base);
372
373 /*!
374 * @brief Configure the system to Stop power mode.
375 *
376 * @param base SMC peripheral base address.
377 * @param option Partial Stop mode option.
378 * @return SMC configuration error code.
379 */
380 status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
381
382 /*!
383 * @brief Configure the system to VLPR power mode.
384 *
385 * @param base SMC peripheral base address.
386 * @return SMC configuration error code.
387 */
388 status_t SMC_SetPowerModeVlpr(SMC_Type *base);
389
390 /*!
391 * @brief Configure the system to VLPW power mode.
392 *
393 * @param base SMC peripheral base address.
394 * @return SMC configuration error code.
395 */
396 status_t SMC_SetPowerModeVlpw(SMC_Type *base);
397
398 /*!
399 * @brief Configure the system to VLPS power mode.
400 *
401 * @param base SMC peripheral base address.
402 * @return SMC configuration error code.
403 */
404 status_t SMC_SetPowerModeVlps(SMC_Type *base);
405 /*!
406 * @brief Configure the system to LLS power mode.
407 *
408 * @param base SMC peripheral base address.
409 * @return SMC configuration error code.
410 */
411 status_t SMC_SetPowerModeLls(SMC_Type *base);
412
413 #if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
414 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
415 /*!
416 * @brief Configure the system to VLLS0 power mode.
417 *
418 * @param base SMC peripheral base address.
419 * @return SMC configuration error code.
420 */
421 status_t SMC_SetPowerModeVlls0(SMC_Type *base);
422 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
423 #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
424 /*!
425 * @brief Configure the system to VLLS2 power mode.
426 *
427 * @param base SMC peripheral base address.
428 * @return SMC configuration error code.
429 */
430 status_t SMC_SetPowerModeVlls2(SMC_Type *base);
431 #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
432 #else
433 /*!
434 * @brief Configure the system to VLLS power mode.
435 *
436 * @param base SMC peripheral base address.
437 * @return SMC configuration error code.
438 */
439 status_t SMC_SetPowerModeVlls(SMC_Type *base);
440 #endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
441
442 /*!
443 * @brief Gets the reset source status which caused a previous reset.
444 *
445 * This function gets the current reset source status. Use source masks
446 * defined in the smc_reset_source_t to get the desired source status.
447 *
448 * Example: To get all reset source statuses.
449 @code
450 resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceAll;
451 @endcode
452
453 Example: To test whether the MCU is reset using Watchdog.
454 @code
455 uint32_t resetStatus;
456
457 resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceWdog;
458 @endcode
459
460 Example: To test multiple reset sources.
461 @code
462 uint32_t resetStatus;
463
464 resetStatus = SMC_GetPreviousResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
465 @endcode
466 *
467 * @param base SMC peripheral base address.
468 * @return All reset source status bit map.
469 */
SMC_GetPreviousResetSources(SMC_Type * base)470 static inline uint32_t SMC_GetPreviousResetSources(SMC_Type *base)
471 {
472 return base->SRS;
473 }
474
475 /*!
476 * @brief Gets the sticky reset source status.
477 *
478 * This function gets the current reset source status that has not been cleared
479 * by software for some specific source.
480 *
481 * Example: To get all reset source statuses.
482 @code
483 uint32_t resetStatus;
484
485 resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceAll;
486 @endcode
487
488 Example, To test whether the MCU is reset using Watchdog.
489 @code
490 uint32_t resetStatus;
491
492 resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceWdog;
493 @endcode
494
495 Example To test multiple reset sources.
496 @code
497 uint32_t resetStatus;
498
499 resetStatus = SMC_GetStickyResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
500 @endcode
501 *
502 * @param base SMC peripheral base address.
503 * @return All reset source status bit map.
504 */
SMC_GetStickyResetSources(SMC_Type * base)505 static inline uint32_t SMC_GetStickyResetSources(SMC_Type *base)
506 {
507 return base->SSRS;
508 }
509
510 /*!
511 * @brief Clears the sticky reset source status.
512 *
513 * This function clears the sticky system reset flags indicated by source masks.
514 *
515 * Example: Clears multiple reset sources.
516 @code
517 SMC_ClearStickyResetSources(SMC0, (kSMC_SourceWdog | kSMC_SourcePin));
518 @endcode
519 *
520 * @param base SMC peripheral base address.
521 * @param sourceMasks reset source status bit map
522 */
SMC_ClearStickyResetSources(SMC_Type * base,uint32_t sourceMasks)523 static inline void SMC_ClearStickyResetSources(SMC_Type *base, uint32_t sourceMasks)
524 {
525 base->SSRS = sourceMasks;
526 }
527
528 /*!
529 * @brief Configures the reset pin filter.
530 *
531 * This function sets the reset pin filter including the enablement/disablement and filter width.
532 *
533 * @param base SMC peripheral base address.
534 * @param config Pointer to the configuration structure.
535 */
536 void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config);
537
538 /*!
539 * @brief Sets the system reset interrupt configuration.
540 *
541 * For a graceful shut down, the MSMC supports delaying the assertion of the system
542 * reset for a period of time when the reset interrupt is generated. This function
543 * can be used to enable the interrupt.
544 * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
545 * For example, to delay a reset after the WDOG timeout or PIN reset occurs, configure as follows:
546 * SMC_SetSystemResetInterruptConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
547 *
548 * @param base SMC peripheral base address.
549 * @param intMask Bit mask of the system reset interrupts to enable. See
550 * smc_interrupt_enable_t for details.
551 */
SMC_SetSystemResetInterruptConfig(SMC_Type * base,uint32_t intMask)552 static inline void SMC_SetSystemResetInterruptConfig(SMC_Type *base, uint32_t intMask)
553 {
554 base->SRIE = intMask;
555 }
556
557 /*!
558 * @brief Gets the source status of the system reset interrupt.
559 *
560 * This function gets the source status of the reset interrupt. Use source masks
561 * defined in the smc_interrupt_enable_t to get the desired source status.
562 *
563 * Example: To get all reset interrupt source statuses.
564 @code
565 uint32_t interruptStatus;
566
567 interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntAll;
568 @endcode
569
570 Example: To test whether the reset interrupt of Watchdog is pending.
571 @code
572 uint32_t interruptStatus;
573
574 interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntWdog;
575 @endcode
576
577 Example: To test multiple reset interrupt sources.
578 @code
579 uint32_t interruptStatus;
580
581 interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & (kSMC_IntWdog | kSMC_IntPin);
582 @endcode
583 *
584 * @param base SMC peripheral base address.
585 * @return All reset interrupt source status bit map.
586 */
SMC_GetResetInterruptSourcesStatus(SMC_Type * base)587 static inline uint32_t SMC_GetResetInterruptSourcesStatus(SMC_Type *base)
588 {
589 return base->SRIF;
590 }
591
592 /*!
593 * @brief Clears the source status of the system reset interrupt.
594 *
595 * This function clears the source status of the reset interrupt. Use source masks
596 * defined in the smc_interrupt_enable_t to get the desired source status.
597 *
598 * Example: To clear all reset interrupt source statuses.
599 @code
600 uint32_t interruptStatus;
601
602 MMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntAll);
603 @endcode
604
605 Example, To clear the reset interrupt of Watchdog.
606 @code
607 uint32_t interruptStatus;
608
609 SMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntWdog);
610 @endcode
611
612 Example, To clear multiple reset interrupt sources status.
613 @code
614 uint32_t interruptStatus;
615
616 SMC_ClearResetInterruptSourcesStatus(SMC0, (kSMC_IntWdog | kSMC_IntPin));
617 @endcode
618 *
619 * @param base SMC peripheral base address.
620 * @param intMask All reset interrupt source status bit map to clear.
621 */
SMC_ClearResetInterruptSourcesStatus(SMC_Type * base,uint32_t intMask)622 static inline void SMC_ClearResetInterruptSourcesStatus(SMC_Type *base, uint32_t intMask)
623 {
624 base->SRIF = intMask;
625 }
626
627 #if (defined(FSL_FEATURE_SMC_HAS_CSRE) && FSL_FEATURE_SMC_HAS_CSRE)
628 /*!
629 * @brief Sets the core software reset feature configuration.
630 *
631 * The MSMC supports delaying the assertion of the system reset for a period of time while a core
632 * software reset is generated. This allows software to recover without reseting the entire system.
633 * This function can be used to enable/disable the core software reset feature.
634 * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
635 * For example, to delay a system after the WDOG timeout or PIN core software reset occurs, configure as follows:
636 * SMC_SetCoreSoftwareResetConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
637 *
638 * @param base SMC peripheral base address.
639 * @param intMask Bit mask of the core software reset to enable. See
640 * smc_interrupt_enable_t for details.
641 */
SMC_SetCoreSoftwareResetConfig(SMC_Type * base,uint32_t intMask)642 static inline void SMC_SetCoreSoftwareResetConfig(SMC_Type *base, uint32_t intMask)
643 {
644 base->CSRE = intMask;
645 }
646 #endif /* FSL_FEATURE_SMC_HAS_CSRE */
647
648 /*!
649 * @brief Gets the boot option configuration.
650 *
651 * This function gets the boot option configuration of MSMC.
652 *
653 * @param base SMC peripheral base address.
654 * @return The boot option configuration. 1 means boot option enabled. 0 means not.
655 */
SMC_GetBootOptionConfig(SMC_Type * base)656 static inline uint32_t SMC_GetBootOptionConfig(SMC_Type *base)
657 {
658 return base->MR;
659 }
660
661 #if (defined(FSL_FEATURE_SMC_HAS_FM) && FSL_FEATURE_SMC_HAS_FM)
662 /*!
663 * @brief Sets the force boot option configuration.
664 *
665 * This function sets the focus boot option configuration of MSMC. It can force the corresponding
666 * boot option config to assert on next system reset.
667 *
668 * @param base SMC peripheral base address.
669 * @param val The boot option configuration for next system reset. 1 - boot option enabled. 0 - not.
670 */
SMC_SetForceBootOptionConfig(SMC_Type * base,uint32_t val)671 static inline void SMC_SetForceBootOptionConfig(SMC_Type *base, uint32_t val)
672 {
673 base->FM = val;
674 }
675
676 #if (defined(FSL_FEATURE_SMC_HAS_SRAMLPR) && FSL_FEATURE_SMC_HAS_SRAMLPR)
677 /*!
678 * @brief Enables the conresponding SRAM array in low power retention mode.
679 *
680 * This function enables the conresponding SRAM array in low power retention mode. By default, the SRAM low pwer is
681 * disabled, and only in RUN mode.
682 *
683 * @param base SMC peripheral base address.
684 * @param arrayIdx Index of responding SRAM array.
685 * @param enable Enable the SRAM array in low power retention mode.
686 */
SMC_SRAMEnableLowPowerMode(SMC_Type * base,uint32_t arrayIdx,bool enable)687 static inline void SMC_SRAMEnableLowPowerMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
688 {
689 if (enable)
690 {
691 base->SRAMLPR |= (1U << arrayIdx); /* Set to be placed in RUN modes. */
692 }
693 else
694 {
695 base->SRAMLPR &= ~(1U << arrayIdx); /* Clear to be placed in low power retention mode. */
696 }
697 }
698 #endif /* FSL_FEATURE_SMC_HAS_SRAMLPR */
699
700 #if (defined(FSL_FEATURE_SMC_HAS_SRAMDSR) && FSL_FEATURE_SMC_HAS_SRAMDSR)
701 /*!
702 * @brief Enables the conresponding SRAM array in STOP mode.
703 *
704 * This function enables the conresponding SRAM array in STOP modes. By default, the SRAM is retained in STOP modes.
705 * When disabled, the corresponding SRAM array is powered off in STOP modes.
706 *
707 * @param base SMC peripheral base address.
708 * @param arrayIdx Index of responding SRAM array.
709 * @param enable Enable the SRAM array in STOP modes.
710 */
SMC_SRAMEnableDeepSleepMode(SMC_Type * base,uint32_t arrayIdx,bool enable)711 static inline void SMC_SRAMEnableDeepSleepMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
712 {
713 if (enable)
714 {
715 base->SRAMDSR &= ~(1U << arrayIdx); /* Clear to be retained in STOP modes. */
716 }
717 else
718 {
719 base->SRAMDSR |= (1U << arrayIdx); /* Set to be powered off in STOP modes. */
720 }
721 }
722 #endif /* FSL_FEATURE_SMC_HAS_SRAMDSR */
723
724 #endif /* FSL_FEATURE_SMC_HAS_FM */
725
726 /*! @} */
727
728 #if defined(__cplusplus)
729 }
730 #endif /* __cplusplus*/
731
732 /*! @}*/
733
734 #endif /* FSL_MSMC_H_ */
735
