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Searched refs:shift (Results 1 – 25 of 170) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/gpio_1/
Dfsl_gpio.c84 uint8_t shift = (uint8_t)port % PORT_NUMBERS_EACH_GPIO; in GPIO_PinInit() local
89 base->PDDR &= ~(1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
90 base->PIDR &= ~(1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
95 base->PDDR |= (1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
96 base->PIDR |= (1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
116 uint8_t shift = (uint8_t)port % PORT_NUMBERS_EACH_GPIO; in GPIO_PinWrite() local
121 base->PCOR = 1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT)); in GPIO_PinWrite()
125 base->PSOR = 1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT)); in GPIO_PinWrite()
142 uint8_t shift = (uint8_t)port % PORT_NUMBERS_EACH_GPIO; in GPIO_PortSet() local
145 base->PSOR = ((uint32_t)mask << (shift * PIN_NUMBERS_EACH_PORT)); in GPIO_PortSet()
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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Include/
Darm_nnsupportfunctions.h795 …TIC_FORCEINLINE q31_t arm_nn_requantize(const q31_t val, const q31_t multiplier, const q31_t shift) in arm_nn_requantize() argument
797 …ivide_by_power_of_two(arm_nn_doubling_high_mult_no_sat(val * (1 << LEFT_SHIFT(shift)), multiplier), in arm_nn_requantize()
798 RIGHT_SHIFT(shift)); in arm_nn_requantize()
848 const int32x4_t shift = vdupq_n_s32(-exponent); in arm_divide_by_power_of_two_mve() local
849 const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); in arm_divide_by_power_of_two_mve()
851 return vrshlq_s32(fixed_up_dividend, shift); in arm_divide_by_power_of_two_mve()
863 …INLINE int32x4_t arm_requantize_mve(const int32x4_t val, const q31_t multiplier, const q31_t shift) in arm_requantize_mve() argument
866 …ing_high_mult_mve(vshlq_s32(val, vdupq_n_s32(LEFT_SHIFT(shift))), multiplier), RIGHT_SHIFT(shift)); in arm_requantize_mve()
876 const int32x4_t shift = -exponent; in arm_divide_by_power_of_two_mve_32x4() local
877 const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); in arm_divide_by_power_of_two_mve_32x4()
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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/FilteringFunctions/
Darm_biquad_cascade_df1_32x64_q31.c193 int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ in arm_biquad_cas_df1_32x64_q31_scalar() local
246 Yn1 = acc << shift; in arm_biquad_cas_df1_32x64_q31_scalar()
297 int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ in arm_biquad_cas_df1_32x64_q31() local
358 Yn1 = asrl(Yn1, -shift); in arm_biquad_cas_df1_32x64_q31()
380 Yn1 = asrl(Yn1, -shift); in arm_biquad_cas_df1_32x64_q31()
393 Yn1 = asrl(Yn1, -shift); in arm_biquad_cas_df1_32x64_q31()
403 Yn1 = asrl(Yn1, -shift); in arm_biquad_cas_df1_32x64_q31()
413 Yn1 = asrl(Yn1, -shift); in arm_biquad_cas_df1_32x64_q31()
437 Yn1 = asrl(Yn1, -shift); in arm_biquad_cas_df1_32x64_q31()
453 Yn1 = asrl(Yn1, -shift); in arm_biquad_cas_df1_32x64_q31()
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Darm_biquad_cascade_df1_q15.c69 int shift; in arm_biquad_cascade_df1_q15() local
79 shift = (15 - postShift) - 32; in arm_biquad_cascade_df1_q15()
121 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
126 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
134 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
140 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
171 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
181 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
195 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
205 acc = sqrshrl_sat48(acc, shift); in arm_biquad_cascade_df1_q15()
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Darm_biquad_cascade_df1_q31.c68 int shift; in arm_biquad_cascade_df1_q31() local
80 shift = (postShift + 1 + 8); in arm_biquad_cascade_df1_q31()
123 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
130 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
164 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
181 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
195 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
202 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
231 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
238 acc = lsll(acc, shift); in arm_biquad_cascade_df1_q31()
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Darm_biquad_cascade_df1_fast_q31.c76 int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ in arm_biquad_cascade_df1_fast_q31() local
128 Yn2 = acc << shift; in arm_biquad_cascade_df1_fast_q31()
154 Yn1 = acc << shift; in arm_biquad_cascade_df1_fast_q31()
180 Yn2 = acc << shift; in arm_biquad_cascade_df1_fast_q31()
212 Yn1 = acc << shift; in arm_biquad_cascade_df1_fast_q31()
258 acc = acc << shift; in arm_biquad_cascade_df1_fast_q31()
/hal_nxp-latest/mcux/mcux-sdk/drivers/wuu/
Dfsl_wuu.c203 uint8_t shift; in WUU_SetPinFilterConfig() local
208 shift = (filterIndex - 1U) * 8U; in WUU_SetPinFilterConfig()
210 filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTE_FIELD_MASK, shift); in WUU_SetPinFilterConfig()
211 filterReg |= WUU_SET_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD(config->edge), shift); in WUU_SetPinFilterConfig()
215 filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD_MASK, shift); in WUU_SetPinFilterConfig()
216 filterReg |= WUU_SET_BIT_FIELD_IN_REG(config->pinIndex, shift); in WUU_SetPinFilterConfig()
219 shift = (filterIndex - 1U) * 2U; in WUU_SetPinFilterConfig()
221 eventReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FDC_REG_FILTC_FIELD_MASK, shift); in WUU_SetPinFilterConfig()
222 eventReg |= WUU_SET_BIT_FIELD_IN_REG(config->event, shift); in WUU_SetPinFilterConfig()
226 shift = (filterIndex - 1U) * 1U; in WUU_SetPinFilterConfig()
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/hal_nxp-latest/mcux/mcux-sdk/middleware/mmcau/asm-cm0p/src/
Dmmcau_sha1_functions.s199 str r5, [r2] @ shift registers
207 str r5, [r2] @ shift registers
215 str r5, [r2] @ shift registers
223 str r5, [r2] @ shift registers
231 str r5, [r2] @ shift registers
239 str r5, [r2] @ shift registers
247 str r5, [r2] @ shift registers
255 str r5, [r2] @ shift registers
263 str r5, [r2] @ shift registers
271 str r5, [r2] @ shift registers
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Dmmcau_sha256_functions.s225 str r1, [r5] @ shift registers
237 str r1, [r5] @ shift registers
249 str r1, [r5] @ shift registers
261 str r1, [r5] @ shift registers
273 str r1, [r5] @ shift registers
285 str r1, [r5] @ shift registers
297 str r1, [r5] @ shift registers
309 str r1, [r5] @ shift registers
321 str r1, [r5] @ shift registers
333 str r1, [r5] @ shift registers
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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/DistanceFunctions/
Darm_boolean_distance_template.h102 int shift; in FUNC() local
150 shift = 0; in FUNC()
151 while(shift < 32) in FUNC()
170 shift ++; in FUNC()
253 int shift; in FUNC() local
372 shift = 0; in FUNC()
373 while(shift < 32) in FUNC()
392 shift ++; in FUNC()
473 int shift; in FUNC() local
479 shift = 0; in FUNC()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/sdu/
Dcis_table.c204 static uint32_t modify2(uint32_t tmp, uint32_t mask, uint32_t shift, uint32_t val) in modify2() argument
206 mask >>= shift; in modify2()
208 val <<= shift; // Now move val to field off in modify2()
209 mask <<= shift; // mask moves too to field off in modify2()
215 void rmw2(volatile uint32_t *addr, uint32_t mask, uint32_t shift, uint32_t val) in rmw2() argument
217 *addr = modify2(*addr, mask, shift, val); in rmw2()
225 static uint32_t extract2(uint32_t data, uint32_t mask, uint32_t shift) in extract2() argument
229 tmp >>= shift; // shift to 0 in extract2()
230 mask >>= shift; in extract2()
235 static uint32_t rd2(volatile uint32_t *addr, uint32_t mask, uint32_t shift) in rd2() argument
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/hal_nxp-latest/mcux/mcux-sdk/drivers/aipstz/
Dfsl_aipstz.c33 uint32_t shift = (uint32_t)master & 0xFFU; in AIPSTZ_SetMasterPriviledgeLevel() local
34 base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift); in AIPSTZ_SetMasterPriviledgeLevel()
48 uint32_t shift = (uint32_t)peripheral & 0xFFU; in AIPSTZ_SetPeripheralAccessControl() local
50 *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift); in AIPSTZ_SetPeripheralAccessControl()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/SoftmaxFunctions/
Darm_softmax_q7.c65 uint8_t shift; in arm_softmax_q7() local
89 shift = (uint8_t)__USAT(vec_in[i] - base, 3); in arm_softmax_q7()
90 sum += 0x1 << shift; in arm_softmax_q7()
100 shift = (uint8_t)__USAT(13 + base - vec_in[i], 5); in arm_softmax_q7()
101 p_out[i] = (q7_t)__SSAT((output_base >> shift), 8); in arm_softmax_q7()
Darm_softmax_q15.c65 uint8_t shift; in arm_softmax_q15() local
88 shift = (uint8_t)__USAT(vec_in[i] - base, 5); in arm_softmax_q15()
89 sum += 0x1 << shift; in arm_softmax_q15()
106 shift = (uint8_t)__USAT(17 + base - vec_in[i], 5); in arm_softmax_q15()
107 p_out[i] = (q15_t)__SSAT((output_base >> shift), 16); in arm_softmax_q15()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lmem/
Dfsl_lmem_cache.c373 uint32_t shift = LMEM_CACHEMODE_WIDTH * (uint32_t)region; /* Region shift. */ in LMEM_CodeCacheDemoteRegion() local
374 uint32_t mask = ((uint32_t)LMEM_CACHEMODE_MASK_UNIT) << shift; /* Region mask. */ in LMEM_CodeCacheDemoteRegion()
377 if ((uint32_t)cacheMode >= ((mode & mask) >> shift)) in LMEM_CodeCacheDemoteRegion()
384 base->PCCRMR = (mode & ~mask) | ((uint32_t)cacheMode) << shift; in LMEM_CodeCacheDemoteRegion()
730 uint32_t shift = LMEM_CACHEMODE_WIDTH * (uint32_t)region; /* Region shift. */ in LMEM_SystemCacheDemoteRegion() local
734 mask = temp << shift; in LMEM_SystemCacheDemoteRegion()
737 if ((uint32_t)cacheMode >= ((mode & mask) >> shift)) in LMEM_SystemCacheDemoteRegion()
744 base->PSCRMR = (mode & ~mask) | (((uint32_t)cacheMode) << shift); in LMEM_SystemCacheDemoteRegion()
/hal_nxp-latest/mcux/mcux-sdk/components/codec/tfa9xxx/vas_tfa_drv/
Dtfa2_haptic.h13 #define TFA2_HAPTIC_FP_INT(value, shift) ((value) >> (shift)) argument
14 #define TFA2_HAPTIC_FP_FRAC(value, shift) ((((value) & ((1 << (shift)) - 1)) * 1000) >> (shift)) argument
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/drivers/
Dfsl_port.c69 …uint32_t shift = (uint32_t)module & ~(PORT_PINSEL_REG_OFFSET | (PORT_MODULEPS_BITWIDTH_MASK << POR… in PORT_SetPinSelect() local
75 pinSelReg = SIM->PINSEL0 & ~ (uint32_t)(((1UL << bitwidth) - 1U) << shift); in PORT_SetPinSelect()
76 SIM->PINSEL0 = pinSelReg | ((uint32_t)pin << shift); in PORT_SetPinSelect()
80 pinSelReg = SIM->PINSEL1 & ~ (uint32_t)(((1UL << bitwidth) - 1U) << shift); in PORT_SetPinSelect()
81 SIM->PINSEL1 = pinSelReg | ((uint32_t)pin << shift); in PORT_SetPinSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/drivers/
Dfsl_port.c69 …uint32_t shift = (uint32_t)module & ~((uint32_t)PORT_PINSEL_REG_OFFSET | ((uint32_t)PORT_MODULEPS_… in PORT_SetPinSelect() local
75 pinSelReg = SIM->PINSEL0 & ~ (((1UL << bitwidth) - 1U) << shift); in PORT_SetPinSelect()
76 SIM->PINSEL0 = pinSelReg | ((uint32_t)pin << shift); in PORT_SetPinSelect()
80 pinSelReg = SIM->PINSEL1 & ~ (((1UL << bitwidth) - 1U) << shift); in PORT_SetPinSelect()
81 SIM->PINSEL1 = pinSelReg | ((uint32_t)pin << shift); in PORT_SetPinSelect()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/BasicMathFunctions/
Darm_scale_q7.c62 int8_t shift, in arm_scale_q7() argument
82 vecDst = vqshlq_r(vecDst, shift + 1); in arm_scale_q7()
103 vecDst = vqshlq_r(vecDst, shift + 1); in arm_scale_q7()
113 int8_t shift, in arm_scale_q7() argument
118 int8_t kShift = 7 - shift; /* Shift to apply after scaling */ in arm_scale_q7()
Darm_scale_q15.c61 int8_t shift, in arm_scale_q15() argument
81 vecDst = vqshlq_r(vecDst, shift + 1); in arm_scale_q15()
102 vecDst = vqshlq_r(vecDst, shift + 1); in arm_scale_q15()
113 int8_t shift, in arm_scale_q15() argument
118 int8_t kShift = 15 - shift; /* Shift to apply after scaling */ in arm_scale_q15()
Darm_scale_q31.c61 int8_t shift, in arm_scale_q31() argument
79 vecDst = vqshlq_r(vecDst, shift + 1); in arm_scale_q31()
100 vecDst = vqshlq_r(vecDst, shift + 1); in arm_scale_q31()
109 int8_t shift, in arm_scale_q31() argument
115 int8_t kShift = shift + 1; /* Shift to apply after scaling */ in arm_scale_q31()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/ConvolutionFunctions/
Darm_nn_depthwise_conv_s8_core.c134 const int32x4_t shift = vldrwq_s32(out_shift); in arm_nn_depthwise_conv_s8_core() local
138 out_0 = arm_requantize_mve_32x4(out_0, mult, shift); in arm_nn_depthwise_conv_s8_core()
139 out_1 = arm_requantize_mve_32x4(out_1, mult, shift); in arm_nn_depthwise_conv_s8_core()
185 const int32x4_t shift = vldrwq_z_s32(out_shift, p); in arm_nn_depthwise_conv_s8_core() local
187 col_0_sum = arm_requantize_mve_32x4(col_0_sum, mult, shift); in arm_nn_depthwise_conv_s8_core()
188 col_1_sum = arm_requantize_mve_32x4(col_1_sum, mult, shift); in arm_nn_depthwise_conv_s8_core()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Source/NNSupportFunctions/
Darm_nn_depthwise_conv_nt_t_padded_s8.c112 const int32x4_t shift = vldrwq_s32(out_shift); in arm_nn_depthwise_conv_nt_t_padded_s8() local
116 out_0 = arm_requantize_mve_32x4(out_0, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
123 out_1 = arm_requantize_mve_32x4(out_1, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
129 out_2 = arm_requantize_mve_32x4(out_2, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
135 out_3 = arm_requantize_mve_32x4(out_3, mult, shift); in arm_nn_depthwise_conv_nt_t_padded_s8()
Darm_nn_depthwise_conv_nt_t_s8.c114 const int32x4_t shift = vldrwq_s32(out_shift); in arm_nn_depthwise_conv_nt_t_s8() local
119 out_0 = arm_requantize_mve_32x4(out_0, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
125 out_1 = arm_requantize_mve_32x4(out_1, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
131 out_2 = arm_requantize_mve_32x4(out_2, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
137 out_3 = arm_requantize_mve_32x4(out_3, mult, shift); in arm_nn_depthwise_conv_nt_t_s8()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/
Dgic_v3.h488 uint32_t shift = (IRQn % 16U) << 1U; in GIC_SetConfiguration() local
490 icfgr &= (~(3U << shift)); in GIC_SetConfiguration()
491 icfgr |= ( int_config << shift); in GIC_SetConfiguration()
628 uint32_t shift = (IRQn % 32U); in GIC_SetGroup() local
630 igroupr &= (~(1U << shift)); in GIC_SetGroup()
631 igroupr |= ( (group & 1U) << shift); in GIC_SetGroup()
640 uint32_t shift = (IRQn % 32U); in GIC_SetRedistGroup() local
646 igroupr &= (~(1U << shift)); in GIC_SetRedistGroup()
647 igroupr |= ( (group & 1U) << shift); in GIC_SetRedistGroup()

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