Home
last modified time | relevance | path

Searched refs:scg_sirc_config_t (Results 1 – 25 of 67) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z512/
Dclock_config.c69 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
173 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
283 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
385 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
Dclock_config.h56 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
97 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
138 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.h53 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
91 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
129 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
Dclock_config.c73 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
146 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
246 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
354 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
/hal_nxp-latest/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c71 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
173 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
285 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
405 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN = {
Dclock_config.h57 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
98 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
139 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dclock_config.h57 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
98 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
139 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
Dclock_config.c87 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
201 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
332 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
448 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke16z/
Dclock_config.c72 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
173 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
281 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
Dclock_config.h57 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
98 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke15z/
Dclock_config.c73 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
172 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
277 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
Dclock_config.h58 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
99 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z/
Dclock_config.c70 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, in CLOCK_CONFIG_FircSafeConfig()
168 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
269 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
Dclock_config.h56 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
97 extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.h420 } scg_sirc_config_t; typedef
922 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.h416 } scg_sirc_config_t; typedef
918 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.h408 } scg_sirc_config_t; typedef
910 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.h431 } scg_sirc_config_t; typedef
965 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.h440 } scg_sirc_config_t; typedef
996 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.h466 } scg_sirc_config_t; typedef
996 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.h432 } scg_sirc_config_t; typedef
966 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.h448 } scg_sirc_config_t; typedef
1004 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.h473 } scg_sirc_config_t; typedef
1003 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/
Dfsl_clock.h424 } scg_sirc_config_t; typedef
963 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.h447 } scg_sirc_config_t; typedef
1003 status_t CLOCK_InitSirc(const scg_sirc_config_t *config);

123