region (reference) in projects: hal_nxp-latest

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Searched refs:region (Results 1 – 25 of 643) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/iee_apc/
D	fsl_iee_apc.c	79 status_t IEE_APC_SetRegionConfig(IEE_APC_Type base, iee_apc_region_t region, uint32_t startAddr, u… in IEE_APC_SetRegionConfig() argument 96 if (region == kIEE_APC_Region0) in IEE_APC_SetRegionConfig() 109 if (region == kIEE_APC_Region1) in IEE_APC_SetRegionConfig() 121 if (region == kIEE_APC_Region2) in IEE_APC_SetRegionConfig() 133 if (region == kIEE_APC_Region3) in IEE_APC_SetRegionConfig() 145 if (region == kIEE_APC_Region4) in IEE_APC_SetRegionConfig() 157 if (region == kIEE_APC_Region5) in IEE_APC_SetRegionConfig() 169 if (region == kIEE_APC_Region6) in IEE_APC_SetRegionConfig() 181 if (region == kIEE_APC_Region7) in IEE_APC_SetRegionConfig() 208 status_t IEE_APC_LockRegionConfig(IEE_APC_Type base, iee_apc_region_t region, uint8_t domain) in IEE_APC_LockRegionConfig() argument [all …]
D	fsl_iee_apc.h	94 status_t IEE_APC_SetRegionConfig(IEE_APC_Type base, iee_apc_region_t region, uint32_t startAddr, u… 108 status_t IEE_APC_LockRegionConfig(IEE_APC_Type base, iee_apc_region_t region, uint8_t domain); 122 status_t IEE_APC_SetAccessControl(IEE_APC_Type base, iee_apc_region_t region, bool allowNonSecure,… 137 status_t IEE_APC_LockRegionConfig(IEE_APC_Type base, iee_apc_region_t region, iee_apc_domain_t dom… 148 void IEE_APC_RegionEnable(IEE_APC_Type base, iee_apc_region_t region); 159 void IEE_APC_RegionDisable(IEE_APC_Type base, iee_apc_region_t region);
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
D	fsl_iped.c	11 iped_region_t region, in IPED_SetRegionAddressRange() argument 16 if (IPED_IsRegionLocked(base, region)) in IPED_SetRegionAddressRange() 22 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2UL))) \| in IPED_SetRegionAddressRange() 23 (IPED_RW_ENABLE_VAL << (region * 2UL)); in IPED_SetRegionAddressRange() 25 …g_start = (__IO uint32_t )(((uint32_t) & (base->IPEDCTX0START)) + (IPED_CTX_REG_OFFSET region)); in IPED_SetRegionAddressRange() 26 …reg_end = (__IO uint32_t )(((uint32_t) & (base->IPEDCTX0END)) + (IPED_CTX_REG_OFFSET region)); in IPED_SetRegionAddressRange() 34 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2UL))) \| in IPED_SetRegionAddressRange() 35 (IPED_RW_DISABLE_VAL << (region * 2UL)); in IPED_SetRegionAddressRange() 40 status_t IPED_SetRegionEnable(FLEXSPI_Type *base, iped_region_t region, bool enable) in IPED_SetRegionEnable() argument 43 if (IPED_IsRegionLocked(base, region)) in IPED_SetRegionEnable() [all …]
D	fsl_iped.h	118 static inline void IPED_SetLock(FLEXSPI_Type base, iped_region_t region) in IPED_SetLock() argument 121 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region 2UL))) \| in IPED_SetLock() 122 (IPED_RW_ENABLE_VAL << (region * 2UL)); in IPED_SetLock() 124 …DCTXCTRL[1] = (base->IPEDCTXCTRL[1] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_MASK << (region * 2UL))) \| in IPED_SetLock() 125 (IPED_RW_DISABLE_VAL << (region * 2UL)); in IPED_SetLock() 127 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2UL))) \| in IPED_SetLock() 128 (IPED_RW_DISABLE_VAL << (region * 2UL)); in IPED_SetLock() 137 static inline bool IPED_IsRegionLocked(FLEXSPI_Type base, iped_region_t region) in IPED_IsRegionLocked() argument 139 uint32_t freeze_mask = (FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_MASK << (region 2UL)); in IPED_IsRegionLocked() 140 uint32_t rw_enable_mask = (IPED_RW_ENABLE_VAL << (region * 2UL)); in IPED_IsRegionLocked() [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
D	fsl_iped.c	11 iped_region_t region, in IPED_SetRegionAddressRange() argument 16 if (IPED_IsRegionLocked(base, region)) in IPED_SetRegionAddressRange() 22 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2UL))) \| in IPED_SetRegionAddressRange() 23 (IPED_RW_ENABLE_VAL << (region * 2UL)); in IPED_SetRegionAddressRange() 25 …g_start = (__IO uint32_t )(((uint32_t) & (base->IPEDCTX0START)) + (IPED_CTX_REG_OFFSET region)); in IPED_SetRegionAddressRange() 26 …reg_end = (__IO uint32_t )(((uint32_t) & (base->IPEDCTX0END)) + (IPED_CTX_REG_OFFSET region)); in IPED_SetRegionAddressRange() 34 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2UL))) \| in IPED_SetRegionAddressRange() 35 (IPED_RW_DISABLE_VAL << (region * 2UL)); in IPED_SetRegionAddressRange() 40 status_t IPED_SetRegionEnable(FLEXSPI_Type *base, iped_region_t region, bool enable) in IPED_SetRegionEnable() argument 43 if (IPED_IsRegionLocked(base, region)) in IPED_SetRegionEnable() [all …]
D	fsl_iped.h	118 static inline void IPED_SetLock(FLEXSPI_Type base, iped_region_t region) in IPED_SetLock() argument 121 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region 2UL))) \| in IPED_SetLock() 122 (IPED_RW_ENABLE_VAL << (region * 2UL)); in IPED_SetLock() 124 …DCTXCTRL[1] = (base->IPEDCTXCTRL[1] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_MASK << (region * 2UL))) \| in IPED_SetLock() 125 (IPED_RW_DISABLE_VAL << (region * 2UL)); in IPED_SetLock() 127 …DCTXCTRL[0] = (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2UL))) \| in IPED_SetLock() 128 (IPED_RW_DISABLE_VAL << (region * 2UL)); in IPED_SetLock() 137 static inline bool IPED_IsRegionLocked(FLEXSPI_Type base, iped_region_t region) in IPED_IsRegionLocked() argument 139 uint32_t freeze_mask = (FLEXSPI_IPEDCTXCTRL_CTX0_FREEZE1_MASK << (region 2UL)); in IPED_IsRegionLocked() 140 uint32_t rw_enable_mask = (IPED_RW_ENABLE_VAL << (region * 2UL)); in IPED_IsRegionLocked() [all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/prince/
D	fsl_prince.c	180 status_t PRINCE_GenNewIV(prince_region_t region, uint8_t iv_code, bool store, flash_config_t flas… in PRINCE_GenNewIV() argument 194 …sicKey(PUF, (puf_key_index_register_t)(uint32_t)((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region), 8, in PRINCE_GenNewIV() 205 (((uint32_t)region * sizeof(cfpa_cfg_iv_code_t))) + 4U], in PRINCE_GenNewIV() 251 status_t PRINCE_LoadIV(prince_region_t region, uint8_t iv_code) in PRINCE_LoadIV() argument 264 if (((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region) == (uint32_t)keyIndex) in PRINCE_LoadIV() 270 (void)PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); in PRINCE_LoadIV() 305 …prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t flash_context, bo… in PRINCE_SetEncryptForAddressRange() argument 345 status = PRINCE_GenNewIV((prince_region_t)region, &prince_iv_code[0], true, flash_context); in PRINCE_SetEncryptForAddressRange() 352 status = PRINCE_LoadIV((prince_region_t)region, &prince_iv_code[0]); in PRINCE_SetEncryptForAddressRange() 395 (void)PRINCE_GetRegionSREnable(PRINCE, (prince_region_t)region, &srEnableRegisterActual); in PRINCE_SetEncryptForAddressRange() [all …]
D	fsl_prince.h	271 status_t PRINCE_GenNewIV(prince_region_t region, uint8_t iv_code, bool store, flash_config_t flas… 286 status_t PRINCE_LoadIV(prince_region_t region, uint8_t iv_code); 315 …prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t flash_context, bo… 330 status_t PRINCE_GetRegionSREnable(PRINCE_Type base, prince_region_t region, uint32_t sr_enable); 344 status_t PRINCE_GetRegionBaseAddress(PRINCE_Type base, prince_region_t region, uint32_t region_ba… 355 status_t PRINCE_SetRegionIV(PRINCE_Type base, prince_region_t region, const uint8_t iv[8]); 366 status_t PRINCE_SetRegionBaseAddress(PRINCE_Type base, prince_region_t region, uint32_t region_bas… 377 status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable);
/hal_nxp-latest/mcux/mcux-sdk/drivers/iped/
D	fsl_iped.c	28 iped_region_t region, in IPED_SetRegionAddressRange() argument 37 …if ((base->IPEDCTXCTRL[1] & (FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK << (region * 2u)))… in IPED_SetRegionAddressRange() 38 (IPED_RW_ENABLE_VAL << (region * 2u))) in IPED_SetRegionAddressRange() 46 … (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2u))) \| in IPED_SetRegionAddressRange() 47 (IPED_RW_ENABLE_VAL << (region * 2u)); in IPED_SetRegionAddressRange() 49 switch (region) in IPED_SetRegionAddressRange() 82 … (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2u))) \| in IPED_SetRegionAddressRange() 83 (IPED_RW_DISABLE_VAL << (region * 2u)); in IPED_SetRegionAddressRange() 90 iped_region_t region, in IPED_GetRegionAddressRange() argument 96 switch (region) in IPED_GetRegionAddressRange() [all …]
D	fsl_iped.h	178 static inline void IPED_SetLock(FLEXSPI_Type base, iped_region_t region) in IPED_SetLock() argument 182 … (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region 2u))) \| in IPED_SetLock() 183 (IPED_RW_ENABLE_VAL << (region * 2u)); in IPED_SetLock() 186 … (base->IPEDCTXCTRL[1] & ~(FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK << (region * 2u))) \| in IPED_SetLock() 187 (IPED_RW_DISABLE_VAL << (region * 2u)); in IPED_SetLock() 190 … (base->IPEDCTXCTRL[0] & ~(FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK << (region * 2u))) \| in IPED_SetLock() 191 (IPED_RW_DISABLE_VAL << (region * 2u)); in IPED_SetLock() 205 iped_region_t region, 220 iped_region_t region, 233 status_t IPED_SetRegionIV(FLEXSPI_Type *base, iped_region_t region, const uint8_t iv[8]);
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Source/
D	mmu_armv8a.c	544 const struct ARM_MMU_region region, in add_ARM_MMU_region() argument 547 if (region->size \|\| region->attrs) { in add_ARM_MMU_region() 548 add_map(ptables, region->name, region->base_pa, region->base_va, in add_ARM_MMU_region() 549 region->size, region->attrs \| extra_flags); in add_ARM_MMU_region() 558 const struct ARM_MMU_region region; in setup_page_tables() local 566 region = &MMU_config->mmu_regions[index]; in setup_page_tables() 567 max_va = MAX(max_va, region->base_va + region->size); in setup_page_tables() 568 max_pa = MAX(max_pa, region->base_pa + region->size); in setup_page_tables() 587 region = &MMU_config->mmu_regions[index]; in setup_page_tables() 588 add_ARM_MMU_region(ptables, region, MT_NO_OVERWRITE); in setup_page_tables()
/hal_nxp-latest/mcux/mcux-sdk/drivers/iee/
D	fsl_iee.c	82 void IEE_SetRegionConfig(IEE_Type base, iee_region_t region, iee_config_t config) in IEE_SetRegionConfig() argument 85 base->REGX[region].REGATTR = in IEE_SetRegionConfig() 88 base->REGX[region].REGPO = IEE_REGPO_PGOFF(config->pageOffset); in IEE_SetRegionConfig() 105 … IEE_Type base, iee_region_t region, iee_aes_key_num_t keyNum, const uint8_t key, size_t keySize) in IEE_SetRegionKey() argument 113 to32 = &base->REGX[region].REGKEY1[0]; in IEE_SetRegionKey() 118 to32 = &base->REGX[region].REGKEY2[0]; in IEE_SetRegionKey() 148 void IEE_LockRegionConfig(IEE_Type *base, iee_region_t region) in IEE_LockRegionConfig() argument 150 base->GCFG \|= (uint32_t)(0x1UL << (uint32_t)region); in IEE_LockRegionConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/netc/
D	fsl_netc_endpoint.h	`18 #pragma region api_ep 121 #pragma region netc_ep_stat 142 #pragma region netc_ep_interrupt 167 #pragma region netc_ep_xfer 203 #pragma region netc_ep_datapath 228 #pragma region netc_ep_config 347 #pragma region netc_ep_config 430 #pragma region netc_ep_ntmp 459 #pragma region netc_ep_rx 466 #pragma region Rx Parser [all …]`
D	fsl_netc_mdio.h	`15 #pragma region api_mdio 60 #pragma region netc_mdio_init 110 #pragma region netc_mdio_phy_status 144 #pragma region netc_mdio_init 167 #pragma region netc_mdio_xfer 227 #pragma region netc_mdio_phy_status`
D	fsl_netc.h	`23 #pragma region netc 221 #pragma region netc_hw 398 #pragma region netc_hw_enetc 454 #pragma region netc_hw_port 717 #pragma region netc_hw_port_mac 818 #pragma region netc_hw_table 1177 #pragma region Ingress Port Filter Table 1376 #pragma region Ingress Stream Identification Table 1452 #pragma region Ingress Stream Table 1572 #pragma region Ingress Stream Filter Table [all …]`
D	fsl_netc_timer.h	`15 #pragma region api_timer 57 #pragma region netc_timer_init 133 #pragma region netc_timer_local_sync 222 #pragma region netc_timer_init 265 #pragma region netc_timer_local_sync 417 #pragma region netc_timer_adjust`
D	fsl_netc_switch.h	`18 #pragma region api_swt 121 #pragma region netc_swt_init 217 #pragma region netc_swt_interrupt 229 #pragma region netc_swt_xfer 300 #pragma region netc_swt_datapath 312 #pragma region netc_swt_stat 332 #pragma region netc_swt_init 414 #pragma region netc_swt_ntmp 445 #pragma region netc_swt_interrupt 495 #pragma region netc_swt_rx [all …]`
/hal_nxp-latest/mcux/middleware/wifi_nxp/wifidriver/wpa_supp_if/
D	wifi_nxp_internal.c	254 static void wifi_setup_channel_flag(void channels, int num_chan, region_chan_t region, t_u8 band) in wifi_setup_channel_flag() argument 259 const chan_freq_power_t pchans_get = region->pcfp; in wifi_setup_channel_flag() 262 for (i = 0; i < MAX(num_chan, region->num_cfp); i++) in wifi_setup_channel_flag() 267 if (get_idx >= region->num_cfp) in wifi_setup_channel_flag() 303 region_chan_t region = NULL; in wifi_setup_channel_info() local 308 region = &pmadapter->region_channel[0]; in wifi_setup_channel_info() 310 region = &pmadapter->universal_channel[0]; in wifi_setup_channel_info() 314 wifi_setup_channel_flag(channels, num_channels, region, band); in wifi_setup_channel_info() 319 region = &pmadapter->region_channel[1]; in wifi_setup_channel_info() 321 region = &pmadapter->universal_channel[1]; in wifi_setup_channel_info() [all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/bee/
D	fsl_bee.c	175 status_t BEE_SetRegionKey(BEE_Type base, bee_region_t region, const uint8_t key, size_t keySize) in BEE_SetRegionKey() argument 203 if (region == kBEE_Region0) in BEE_SetRegionKey() 208 else if (region == kBEE_Region1) in BEE_SetRegionKey() 245 status_t BEE_SetRegionNonce(BEE_Type base, bee_region_t region, const uint8_t nonce, size_t nonce… in BEE_SetRegionNonce() argument 259 if (region == kBEE_Region0) in BEE_SetRegionNonce() 264 else if (region == kBEE_Region1) in BEE_SetRegionNonce()
/hal_nxp-latest/mcux/mcux-sdk/drivers/netc/netc_hw/
D	fsl_netc_hw_port.h	`16 #pragma region netc_hw_port 54 #pragma region netc_hw_port_tx 66 #pragma region netc_hw_port_rx 85 #pragma region netc_hw_port 175 #pragma region netc_hw_port_tx 262 #pragma region netc_hw_port_rx 349 #pragma region netc_hw_port_mac`
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/gcc/
D	MIMX8UD7xxxxx_cm33_flash.ld	32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 … 34 …* Memory region from [0x04001000-0x04032000] is reserved for 1st Image Container and 2nd Image Con… 42 /* Memory region from [0x1FFC0000-0x1FFCFFFF] is reserved for shared memory between M33 and DSP. / 43 / Memory region from [0x20008000-0x2002FFFF] is reserved for Fusion DSP / 44 / Memory region from [0x20040000-0x2006FFFF] is reserved for A35 ATF / 45 / Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot / 46 / Memory region(ssram) from [0x20030000-0x20037FFF](size is 32 KiB) is reserved for noncacheable d… 238 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") 285 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/gcc/
D	MIMX8UD5xxxxx_cm33_flash.ld	32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 … 34 …* Memory region from [0x04001000-0x04032000] is reserved for 1st Image Container and 2nd Image Con… 42 /* Memory region from [0x1FFC0000-0x1FFCFFFF] is reserved for shared memory between M33 and DSP. / 43 / Memory region from [0x20008000-0x2002FFFF] is reserved for Fusion DSP / 44 / Memory region from [0x20040000-0x2006FFFF] is reserved for A35 ATF / 45 / Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot / 46 / Memory region(ssram) from [0x20030000-0x20037FFF](size is 32 KiB) is reserved for noncacheable d… 238 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") 285 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/gcc/
D	MIMX8US5xxxxx_cm33_flash.ld	32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 … 34 …* Memory region from [0x04001000-0x04032000] is reserved for 1st Image Container and 2nd Image Con… 42 /* Memory region from [0x1FFC0000-0x1FFCFFFF] is reserved for shared memory between M33 and DSP. / 43 / Memory region from [0x20008000-0x2002FFFF] is reserved for Fusion DSP / 44 / Memory region from [0x20040000-0x2006FFFF] is reserved for A35 ATF / 45 / Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot / 46 / Memory region(ssram) from [0x20030000-0x20037FFF](size is 32 KiB) is reserved for noncacheable d… 238 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") 285 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/gcc/
D	MIMX8US3xxxxx_cm33_flash.ld	32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 … 34 …* Memory region from [0x04001000-0x04032000] is reserved for 1st Image Container and 2nd Image Con… 42 /* Memory region from [0x1FFC0000-0x1FFCFFFF] is reserved for shared memory between M33 and DSP. / 43 / Memory region from [0x20008000-0x2002FFFF] is reserved for Fusion DSP / 44 / Memory region from [0x20040000-0x2006FFFF] is reserved for A35 ATF / 45 / Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot / 46 / Memory region(ssram) from [0x20030000-0x20037FFF](size is 32 KiB) is reserved for noncacheable d… 238 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") 285 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/gcc/
D	MIMX8UD3xxxxx_cm33_flash.ld	32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 … 34 …* Memory region from [0x04001000-0x04032000] is reserved for 1st Image Container and 2nd Image Con… 42 /* Memory region from [0x1FFC0000-0x1FFCFFFF] is reserved for shared memory between M33 and DSP. / 43 / Memory region from [0x20008000-0x2002FFFF] is reserved for Fusion DSP / 44 / Memory region from [0x20040000-0x2006FFFF] is reserved for A35 ATF / 45 / Memory region from [0x20070000-0x2007FFFF] is reserved for ROM API and ROM boot / 46 / Memory region(ssram) from [0x20030000-0x20037FFF](size is 32 KiB) is reserved for noncacheable d… 238 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") 285 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")

12 3 4 5 6 7 8 9 10 >>...26

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