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Searched refs:regValue (Results 1 – 25 of 63) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyksz8081/
Dfsl_phyksz8081.c73 uint16_t regValue = 0; in PHY_KSZ8081_Init() local
82 result = PHY_KSZ8081_READ(handle, PHY_ID1_REG, &regValue); in PHY_KSZ8081_Init()
88 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); in PHY_KSZ8081_Init()
100 result = PHY_KSZ8081_READ(handle, PHY_CONTROL2_REG, &regValue); in PHY_KSZ8081_Init()
105 … result = PHY_KSZ8081_WRITE(handle, PHY_CONTROL2_REG, (regValue | PHY_CTL2_REFCLK_SELECT_MASK)); in PHY_KSZ8081_Init()
131 result = PHY_KSZ8081_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_KSZ8081_Init()
136 regValue &= ~PHY_BCTL_ISOLATE_MASK; in PHY_KSZ8081_Init()
137 result = PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, regValue); in PHY_KSZ8081_Init()
172 uint16_t regValue; in PHY_KSZ8081_GetAutoNegotiationStatus() local
177 result = PHY_KSZ8081_READ(handle, PHY_BASICSTATUS_REG, &regValue); in PHY_KSZ8081_GetAutoNegotiationStatus()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyrtl8211f/
Dfsl_phyrtl8211f.c102 uint16_t regValue = 0U; in PHY_RTL8211F_Init() local
112 result = PHY_RTL8211F_READ(handle, PHY_ID1_REG, &regValue); in PHY_RTL8211F_Init()
118 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); in PHY_RTL8211F_Init()
134 result = PHY_RTL8211F_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_RTL8211F_Init()
139 } while ((regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_RTL8211F_Init()
149 result = PHY_RTL8211F_READ(handle, PHY_RGMII_TX_DELAY_REG, &regValue); in PHY_RTL8211F_Init()
152 regValue |= PHY_RGMII_TX_DELAY_MASK; in PHY_RTL8211F_Init()
153 result = PHY_RTL8211F_WRITE(handle, PHY_RGMII_TX_DELAY_REG, regValue); in PHY_RTL8211F_Init()
165 result = PHY_RTL8211F_READ(handle, PHY_RGMII_RX_DELAY_REG, &regValue); in PHY_RTL8211F_Init()
168 regValue |= PHY_RGMII_RX_DELAY_MASK; in PHY_RTL8211F_Init()
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/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyar8031/
Dfsl_phyar8031.c109 uint16_t regValue = 0; in PHY_AR8031_Init() local
118 result = PHY_AR8031_READ(handle, PHY_ID1_REG, &regValue); in PHY_AR8031_Init()
124 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); in PHY_AR8031_Init()
152 result = PHY_AR8031_MMD_ReadData(handle, &regValue); in PHY_AR8031_Init()
155 …result = PHY_AR8031_MMD_WriteData(handle, (regValue & ~((uint32_t)1 << PHY_MMD_SMARTEEE_LPI_EN_SHI… in PHY_AR8031_Init()
169 result = PHY_AR8031_READ(handle, PHY_DEBUGPORT_DATA_REG, &regValue); in PHY_AR8031_Init()
174 result = PHY_AR8031_WRITE(handle, PHY_DEBUGPORT_DATA_REG, regValue | 0x0100U); in PHY_AR8031_Init()
186 result = PHY_AR8031_READ(handle, PHY_DEBUGPORT_DATA_REG, &regValue); in PHY_AR8031_Init()
191 result = PHY_AR8031_WRITE(handle, PHY_DEBUGPORT_DATA_REG, regValue | 0x8000U); in PHY_AR8031_Init()
201 result = PHY_AR8031_MMD_Read(handle, PHY_MDIO_MMD_PCS, PHY_MDIO_PCS_EEE_CAP, &regValue); in PHY_AR8031_Init()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8741/
Dfsl_phylan8741.c69 uint16_t regValue = 0U; in PHY_LAN8741_Init() local
79 result = PHY_LAN8741_READ(handle, PHY_ID1_REG, &regValue); in PHY_LAN8741_Init()
84 devId = (uint32_t)regValue << 16U; in PHY_LAN8741_Init()
86 result = PHY_LAN8741_READ(handle, PHY_ID2_REG, &regValue); in PHY_LAN8741_Init()
91 devId += regValue; in PHY_LAN8741_Init()
113 result = PHY_LAN8741_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_LAN8741_Init()
118 } while ((counter-- != 0U) && (regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_LAN8741_Init()
143 result = PHY_LAN8741_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_LAN8741_Init()
148 regValue &= PHY_BCTL_ISOLATE_MASK; in PHY_LAN8741_Init()
149 result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, regValue); in PHY_LAN8741_Init()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyrtl8201/
Dfsl_phyrtl8201.c73 uint16_t regValue = 0U; in PHY_RTL8201_Init() local
82 result = PHY_RTL8201_READ(handle, PHY_ID1_REG, &regValue); in PHY_RTL8201_Init()
87 devId = (uint32_t)regValue << 16U; in PHY_RTL8201_Init()
89 result = PHY_RTL8201_READ(handle, PHY_ID2_REG, &regValue); in PHY_RTL8201_Init()
94 devId += regValue; in PHY_RTL8201_Init()
113 result = PHY_RTL8201_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_RTL8201_Init()
118 } while ((regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_RTL8201_Init()
138 result = PHY_RTL8201_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_RTL8201_Init()
142 … (regValue | PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); in PHY_RTL8201_Init()
150 result = PHY_RTL8201_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_RTL8201_Init()
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/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8720a/
Dfsl_phylan8720a.c68 uint16_t regValue = 0U; in PHY_LAN8720A_Init() local
77 result = PHY_LAN8720A_READ(handle, PHY_ID1_REG, &regValue); in PHY_LAN8720A_Init()
83 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); in PHY_LAN8720A_Init()
99 result = PHY_LAN8720A_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_LAN8720A_Init()
104 } while ((counter-- != 0U) && (regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_LAN8720A_Init()
129 result = PHY_LAN8720A_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_LAN8720A_Init()
134 regValue &= PHY_BCTL_ISOLATE_MASK; in PHY_LAN8720A_Init()
135 result = PHY_LAN8720A_WRITE(handle, PHY_BASICCONTROL_REG, regValue); in PHY_LAN8720A_Init()
163 uint16_t regValue; in PHY_LAN8720A_GetAutoNegotiationStatus() local
168 result = PHY_LAN8720A_READ(handle, PHY_SEPCIAL_CONTROL_REG, &regValue); in PHY_LAN8720A_GetAutoNegotiationStatus()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyksz8041/
Dfsl_phyksz8041.c62 uint16_t regValue = 0; in PHY_KSZ8041_Init() local
71 result = PHY_KSZ8041_READ(handle, PHY_ID1_REG, &regValue); in PHY_KSZ8041_Init()
77 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); in PHY_KSZ8041_Init()
107 result = PHY_KSZ8041_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_KSZ8041_Init()
112 regValue &= ~PHY_BCTL_ISOLATE_MASK; in PHY_KSZ8041_Init()
113 result = PHY_KSZ8041_WRITE(handle, PHY_BASICCONTROL_REG, regValue); in PHY_KSZ8041_Init()
142 uint16_t regValue; in PHY_KSZ8041_GetAutoNegotiationStatus() local
147 result = PHY_KSZ8041_READ(handle, PHY_BASICSTATUS_REG, &regValue); in PHY_KSZ8041_GetAutoNegotiationStatus()
150 if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) in PHY_KSZ8041_GetAutoNegotiationStatus()
163 uint16_t regValue; in PHY_KSZ8041_GetLinkStatus() local
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyvsc8541/
Dfsl_phyvsc8541.c78 uint16_t regValue = 0U; in PHY_VSC8541_Init() local
87 result = PHY_VSC8541_READ(handle, PHY_ID1_REG, &regValue); in PHY_VSC8541_Init()
92 devId = regValue << 16U; in PHY_VSC8541_Init()
94 result = PHY_VSC8541_READ(handle, PHY_ID2_REG, &regValue); in PHY_VSC8541_Init()
99 devId += regValue; in PHY_VSC8541_Init()
128 result = PHY_VSC8541_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_VSC8541_Init()
132 … (regValue | PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); in PHY_VSC8541_Init()
140 result = PHY_VSC8541_READ(handle, PHY_BASICCONTROL_REG, &regValue); in PHY_VSC8541_Init()
145 regValue &= PHY_BCTL_ISOLATE_MASK; in PHY_VSC8541_Init()
146 result = PHY_VSC8541_WRITE(handle, PHY_BASICCONTROL_REG, regValue); in PHY_VSC8541_Init()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/netc/
Dfsl_netc_phy_wrapper.c15 uint16_t regValue; in NETC_PHYWriteRegBits() local
18 status = NETC_MDIOC45Read(handle, portAddr, devAddr, regAddr, &regValue); in NETC_PHYWriteRegBits()
21 regValue &= ~mask; in NETC_PHYWriteRegBits()
24 regValue |= val; in NETC_PHYWriteRegBits()
27 status = NETC_MDIOC45Write(handle, portAddr, devAddr, regAddr, regValue); in NETC_PHYWriteRegBits()
50 uint16_t regValue; in NETC_PHYInit() local
72 … NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, &regValue); in NETC_PHYInit()
73 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK; in NETC_PHYInit()
74 } while (regValue == 0x0U); in NETC_PHYInit()
80 NETC_PHYReadReg(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL1, &regValue); in NETC_PHYInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phydp83848/
Dfsl_phydp83848.c52 uint16_t regValue; in PHY_DP83848_Init() local
63 result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, &regValue); in PHY_DP83848_Init()
69 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); in PHY_DP83848_Init()
99 … result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue); in PHY_DP83848_Init()
104 regValue &= ~PHY_BCTL_ISOLATE_MASK; in PHY_DP83848_Init()
105 … result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); in PHY_DP83848_Init()
134 uint16_t regValue; in PHY_DP83848_GetAutoNegotiationStatus() local
139 result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, &regValue); in PHY_DP83848_GetAutoNegotiationStatus()
142 if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) in PHY_DP83848_GetAutoNegotiationStatus()
155 uint16_t regValue; in PHY_DP83848_GetLinkStatus() local
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyaqr113c/
Dfsl_phyaqr113c.c283 uint16_t regValue; in PHY_AQR113C_GetAutoNegotiationStatus() local
285 result = PHY_AQR113C_READ(handle, PHY_MMD_AN, PHY_MMD_AN_STATUS1_REG, &regValue); in PHY_AQR113C_GetAutoNegotiationStatus()
288 if ((AN_STATUS1_COMPLETE & regValue) != 0U) in PHY_AQR113C_GetAutoNegotiationStatus()
305 uint16_t regValue; in PHY_AQR113C_GetLinkStatus() local
307 result = PHY_AQR113C_READ(handle, PHY_MMD_PMAPMD, PHY_MMD_PMAPMD_STATUS1_REG, &regValue); in PHY_AQR113C_GetLinkStatus()
314 if ((STATUS1_LINK_MASK & regValue) == 0x0U) in PHY_AQR113C_GetLinkStatus()
316 result = PHY_AQR113C_READ(handle, PHY_MMD_PMAPMD, PHY_MMD_PMAPMD_STATUS1_REG, &regValue); in PHY_AQR113C_GetLinkStatus()
323 if ((STATUS1_LINK_MASK & regValue) != 0U) in PHY_AQR113C_GetLinkStatus()
331 result = PHY_AQR113C_READ(handle, PHY_MMD_PCS, PHY_MMD_PCS_STATUS1_REG, &regValue); in PHY_AQR113C_GetLinkStatus()
338 if ((PCS_STATUS1_LINK_MASK & regValue) == 0x0U) in PHY_AQR113C_GetLinkStatus()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/xrdc/
Dfsl_xrdc.c576 uint32_t regValue; in XRDC_SetMemAccessConfig() local
592 regValue = 0U; in XRDC_SetMemAccessConfig()
605 regValue <<= XRDC_MRGD_DXACP_WIDTH; in XRDC_SetMemAccessConfig()
607 regValue <<= XRDC_MRGD_DXSEL_WIDTH; in XRDC_SetMemAccessConfig()
609 regValue |= (uint32_t)config->policy[i]; in XRDC_SetMemAccessConfig()
613 regValue |= XRDC_MRGD_W_SE(config->enableSema) | XRDC_MRGD_W_SNUM(config->semaNum); in XRDC_SetMemAccessConfig()
616 base->MRGD[index].MRGD_W[2] = regValue; in XRDC_SetMemAccessConfig()
619 regValue = 0U; in XRDC_SetMemAccessConfig()
625 regValue <<= XRDC_MRGD_DXACP_WIDTH; in XRDC_SetMemAccessConfig()
626 regValue |= (uint32_t)config->policy[i]; in XRDC_SetMemAccessConfig()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/tsi_v4/
Dfsl_tsi_v4.c218 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_EnableInterrupts() local
222 regValue |= TSI_GENCS_TSIIEN_MASK; in TSI_EnableInterrupts()
226 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_EnableInterrupts()
230 regValue |= TSI_GENCS_ESOR_MASK; in TSI_EnableInterrupts()
233 base->GENCS = regValue; /* write value to register */ in TSI_EnableInterrupts()
247 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_DisableInterrupts() local
251 regValue &= (~TSI_GENCS_TSIIEN_MASK); in TSI_DisableInterrupts()
255 regValue |= TSI_GENCS_ESOR_MASK; in TSI_DisableInterrupts()
259 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_DisableInterrupts()
262 base->GENCS = regValue; /* write value to register */ in TSI_DisableInterrupts()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/
Dfsl_tsi_v4.c218 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_EnableInterrupts() local
222 regValue |= TSI_GENCS_TSIIEN_MASK; in TSI_EnableInterrupts()
226 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_EnableInterrupts()
230 regValue |= TSI_GENCS_ESOR_MASK; in TSI_EnableInterrupts()
233 base->GENCS = regValue; /* write value to register */ in TSI_EnableInterrupts()
247 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_DisableInterrupts() local
251 regValue &= (~TSI_GENCS_TSIIEN_MASK); in TSI_DisableInterrupts()
255 regValue |= TSI_GENCS_ESOR_MASK; in TSI_DisableInterrupts()
259 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_DisableInterrupts()
262 base->GENCS = regValue; /* write value to register */ in TSI_DisableInterrupts()
[all …]
Dfsl_tsi_v5.c384 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_EnableInterrupts() local
388 regValue |= TSI_GENCS_TSIIEN_MASK; in TSI_EnableInterrupts()
392 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_EnableInterrupts()
396 regValue |= TSI_GENCS_ESOR_MASK; in TSI_EnableInterrupts()
399 base->GENCS = regValue; /* write value to register */ in TSI_EnableInterrupts()
413 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_DisableInterrupts() local
417 regValue &= (~TSI_GENCS_TSIIEN_MASK); in TSI_DisableInterrupts()
421 regValue |= TSI_GENCS_ESOR_MASK; in TSI_DisableInterrupts()
425 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_DisableInterrupts()
428 base->GENCS = regValue; /* write value to register */ in TSI_DisableInterrupts()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/tsi_v5/
Dfsl_tsi_v5.c391 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_EnableInterrupts() local
395 regValue |= TSI_GENCS_TSIIEN_MASK; in TSI_EnableInterrupts()
399 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_EnableInterrupts()
403 regValue |= TSI_GENCS_ESOR_MASK; in TSI_EnableInterrupts()
406 base->GENCS = regValue; /* write value to register */ in TSI_EnableInterrupts()
420 uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); in TSI_DisableInterrupts() local
424 regValue &= (~TSI_GENCS_TSIIEN_MASK); in TSI_DisableInterrupts()
428 regValue |= TSI_GENCS_ESOR_MASK; in TSI_DisableInterrupts()
432 regValue &= (~TSI_GENCS_ESOR_MASK); in TSI_DisableInterrupts()
435 base->GENCS = regValue; /* write value to register */ in TSI_DisableInterrupts()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_pmu.c149 uint32_t regValue = base->PMU_LDO_AON_ANA; in PMU_StaticAonAnaLdoInit() local
151 regValue &= in PMU_StaticAonAnaLdoInit()
158 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_MASK; in PMU_StaticAonAnaLdoInit()
160 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN(config->enable2mALoad); in PMU_StaticAonAnaLdoInit()
161 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad); in PMU_StaticAonAnaLdoInit()
162 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad); in PMU_StaticAonAnaLdoInit()
163 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN(config->enableStandbyMode); in PMU_StaticAonAnaLdoInit()
165 base->PMU_LDO_AON_ANA = regValue; in PMU_StaticAonAnaLdoInit()
316 uint32_t regValue; in PMU_DisableBandgapSelfBiasAfterPowerUp() local
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_pmu.c149 uint32_t regValue = base->PMU_LDO_AON_ANA; in PMU_StaticAonAnaLdoInit() local
151 regValue &= in PMU_StaticAonAnaLdoInit()
158 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_MASK; in PMU_StaticAonAnaLdoInit()
160 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN(config->enable2mALoad); in PMU_StaticAonAnaLdoInit()
161 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad); in PMU_StaticAonAnaLdoInit()
162 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad); in PMU_StaticAonAnaLdoInit()
163 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN(config->enableStandbyMode); in PMU_StaticAonAnaLdoInit()
165 base->PMU_LDO_AON_ANA = regValue; in PMU_StaticAonAnaLdoInit()
316 uint32_t regValue; in PMU_DisableBandgapSelfBiasAfterPowerUp() local
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_pmu.c149 uint32_t regValue = base->PMU_LDO_AON_ANA; in PMU_StaticAonAnaLdoInit() local
151 regValue &= in PMU_StaticAonAnaLdoInit()
158 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_MASK; in PMU_StaticAonAnaLdoInit()
160 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN(config->enable2mALoad); in PMU_StaticAonAnaLdoInit()
161 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad); in PMU_StaticAonAnaLdoInit()
162 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad); in PMU_StaticAonAnaLdoInit()
163 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN(config->enableStandbyMode); in PMU_StaticAonAnaLdoInit()
165 base->PMU_LDO_AON_ANA = regValue; in PMU_StaticAonAnaLdoInit()
316 uint32_t regValue; in PMU_DisableBandgapSelfBiasAfterPowerUp() local
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_pmu.c149 uint32_t regValue = base->PMU_LDO_AON_ANA; in PMU_StaticAonAnaLdoInit() local
151 regValue &= in PMU_StaticAonAnaLdoInit()
158 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_MASK; in PMU_StaticAonAnaLdoInit()
160 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN(config->enable2mALoad); in PMU_StaticAonAnaLdoInit()
161 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad); in PMU_StaticAonAnaLdoInit()
162 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad); in PMU_StaticAonAnaLdoInit()
163 regValue |= ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN(config->enableStandbyMode); in PMU_StaticAonAnaLdoInit()
165 base->PMU_LDO_AON_ANA = regValue; in PMU_StaticAonAnaLdoInit()
316 uint32_t regValue; in PMU_DisableBandgapSelfBiasAfterPowerUp() local
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/codec/wm8904/
Dfsl_wm8904.c176 uint16_t regValue; in WM8904_ModifyRegister() local
178 result = WM8904_ReadRegister(handle, reg, &regValue); in WM8904_ModifyRegister()
184 regValue &= (uint16_t)~mask; in WM8904_ModifyRegister()
185 regValue |= value; in WM8904_ModifyRegister()
187 return WM8904_WriteRegister(handle, reg, regValue); in WM8904_ModifyRegister()
1237 uint16_t regValue = 0U, regMask = 0U; in WM8904_SetChannelMute() local
1239 regValue = isMute ? 0x180U : 0x80U; in WM8904_SetChannelMute()
1245 ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, regMask, regValue); in WM8904_SetChannelMute()
1251 ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, regMask, regValue); in WM8904_SetChannelMute()
1257 ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_LEFT, regMask, regValue); in WM8904_SetChannelMute()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_soc_src.c47 uint32_t regValue; in SRC_ReleaseCoreReset() local
49 regValue = base->SCR; in SRC_ReleaseCoreReset()
51 if ((regValue & coreMaskArray[((uint32_t)coreName) - 1UL]) == 0UL) in SRC_ReleaseCoreReset()
71 uint32_t regValue; in SRC_SetGlobalSystemResetMode() local
73 regValue = base->SRMR; in SRC_SetGlobalSystemResetMode()
74 …regValue &= ~SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR… in SRC_SetGlobalSystemResetMode()
75 regValue |= SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, resetMode); in SRC_SetGlobalSystemResetMode()
77 base->SRMR = regValue; in SRC_SetGlobalSystemResetMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_soc_src.c47 uint32_t regValue; in SRC_ReleaseCoreReset() local
49 regValue = base->SCR; in SRC_ReleaseCoreReset()
51 if ((regValue & coreMaskArray[((uint32_t)coreName) - 1UL]) == 0UL) in SRC_ReleaseCoreReset()
71 uint32_t regValue; in SRC_SetGlobalSystemResetMode() local
73 regValue = base->SRMR; in SRC_SetGlobalSystemResetMode()
74 …regValue &= ~SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR… in SRC_SetGlobalSystemResetMode()
75 regValue |= SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, resetMode); in SRC_SetGlobalSystemResetMode()
77 base->SRMR = regValue; in SRC_SetGlobalSystemResetMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_soc_src.c47 uint32_t regValue; in SRC_ReleaseCoreReset() local
49 regValue = base->SCR; in SRC_ReleaseCoreReset()
51 if ((regValue & coreMaskArray[((uint32_t)coreName) - 1UL]) == 0UL) in SRC_ReleaseCoreReset()
71 uint32_t regValue; in SRC_SetGlobalSystemResetMode() local
73 regValue = base->SRMR; in SRC_SetGlobalSystemResetMode()
74 …regValue &= ~SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR… in SRC_SetGlobalSystemResetMode()
75 regValue |= SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, resetMode); in SRC_SetGlobalSystemResetMode()
77 base->SRMR = regValue; in SRC_SetGlobalSystemResetMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_soc_src.c47 uint32_t regValue; in SRC_ReleaseCoreReset() local
49 regValue = base->SCR; in SRC_ReleaseCoreReset()
51 if ((regValue & coreMaskArray[((uint32_t)coreName) - 1UL]) == 0UL) in SRC_ReleaseCoreReset()
71 uint32_t regValue; in SRC_SetGlobalSystemResetMode() local
73 regValue = base->SRMR; in SRC_SetGlobalSystemResetMode()
74 …regValue &= ~SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR… in SRC_SetGlobalSystemResetMode()
75 regValue |= SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, resetMode); in SRC_SetGlobalSystemResetMode()
77 base->SRMR = regValue; in SRC_SetGlobalSystemResetMode()

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