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Searched refs:refDiv2 (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8mq/
Dclock_config.c78 .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */
88 .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */
98 .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
Dsystem_MIMX8MQ5_cm4.c125 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK, in GetSSCGPllFreq() local
161 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in GetSSCGPllFreq()
165 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
Dsystem_MIMX8MD7_cm4.c125 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK, in GetSSCGPllFreq() local
161 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in GetSSCGPllFreq()
165 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
Dsystem_MIMX8MD6_cm4.c125 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK, in GetSSCGPllFreq() local
161 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in GetSSCGPllFreq()
165 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
Dsystem_MIMX8MQ6_cm4.c125 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK, in GetSSCGPllFreq() local
161 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in GetSSCGPllFreq()
165 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
Dsystem_MIMX8MQ7_cm4.c125 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK, in GetSSCGPllFreq() local
161 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in GetSSCGPllFreq()
165 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in GetSSCGPllFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.c863 assert(config->refDiv2 != 0U); in CLOCK_InitSSCGPll()
896 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) | in CLOCK_InitSSCGPll()
923 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
944 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
948 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h1004 …uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54M… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.c863 assert(config->refDiv2 != 0U); in CLOCK_InitSSCGPll()
896 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) | in CLOCK_InitSSCGPll()
923 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
944 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
948 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h1004 …uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54M… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.c863 assert(config->refDiv2 != 0U); in CLOCK_InitSSCGPll()
896 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) | in CLOCK_InitSSCGPll()
923 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
944 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
948 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h1004 …uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54M… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.c863 assert(config->refDiv2 != 0U); in CLOCK_InitSSCGPll()
896 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) | in CLOCK_InitSSCGPll()
923 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
944 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
948 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h1004 …uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54M… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
Dfsl_clock.c863 assert(config->refDiv2 != 0U); in CLOCK_InitSSCGPll()
896 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) | in CLOCK_InitSSCGPll()
923 …uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
944 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
948 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2; in CLOCK_GetSSCGPllFreq()
Dfsl_clock.h1004 …uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54M… member