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Searched refs:r3 (Results 1 – 25 of 231) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/middleware/mmcau/asm-cm0p/src/
Dmmcau_aes_functions.s69 mov r3, r8
74 push {r3-r7} @ store high regs
76 ldr r3, =set_key_reg_data @ prepare for set_key reg load
99 # r3 | key_sch[0+8i] / scratch
113 # ldmia r3, {r3-r7}
114 mov r1, r3 @ store r3 in scratch r1 to be interruptible
115 adds r3, #1<<2 @ move r3 by 4 bytes
116 ldmia r3!, {r4-r7} @ ldmia without r3
117 ldr r3, [r1] @ load to r3 from scratch address
118 mov r8, r3 @ r8 = *rcon
[all …]
Dmmcau_md5_functions.s70 str r3, [r0, #2<<2]
120 # ldr r3,[r2, #2<<2]
137 # r3 | c
147 ands r5, r3 @ b & c
162 ands r6, r3 @ ~a & c
178 add r3, r5 @ c += F(d,a,b)
180 add r3, r6 @ c += msg_data[2]
182 add r3, r5 @ c += md5_t[2]
184 rors r3, r6 @ ROTL(c,17)
185 add r3, r4 @ c = d + ROTL(c,17)
[all …]
Dmmcau_sha256_functions.s63 ldr r3, =sha256_initial_h
64 ldmia r3!, {r4-r7} @ load sha256_initial_h[0-3]
72 ldmia r3!, {r4-r7} @ load sha256_initial_h[4-7]
137 mov r3, r8
142 push {r0-r2, r3-r7} @ store *input, num_blks, *output, high regs
202 # r3 | mmcau_3_cmds(ADRA+CA7,HASH+HF2T,HASH+HF2C)
220 str r3, [r5] @ +h, +SIGMA1(e), +Ch(e,f,g)
233 str r3, [r5] @ +h, +SIGMA1(e), +Ch(e,f,g)
245 str r3, [r5] @ +h, +SIGMA1(e), +Ch(e,f,g)
257 str r3, [r5] @ +h, +SIGMA1(e), +Ch(e,f,g)
[all …]
Dmmcau_sha1_functions.s132 ldmia r2!, {r3-r7} @ load sha1_state[0-4]
133 # stmia r1!, {r3-r7} @ store in CA[0-4]
134 str r3, [r1, #0<<2] @ expand stmia into str to be interruptible
148 # stmia r2!, {r3-r7} @ store sha1_state[0-4]
149 str r3, [r2, #0<<2] @ expand stmia into str to be interruptible
158 rors r3, r1 @ ROTL(a,5)
159 str r3, [r4] @ store in CAA
187 # r3 | scratch
322 movs r3, #31 @ set the amount to rotate
345 # r3 | amount to rotate = #31
[all …]
/hal_nxp-latest/mcux/mcux-sdk/middleware/mmcau/asm-cm4-cm7/src/
Dmmcau_aes_functions.s56 # r3 = scratch
99 ldmia r0, {r1,r3,r8-r9} @ copy key[4-7]
101 rev r3, r3 @ byte reverse
104 stmia r2!, {r1,r3,r8-r9} @ to key_sch[4-7]
127 eor r3, r1 @ key_sch[5]^key_sch[12]
128 eor r8, r3 @ key_sch[6]^key_sch[13]
130 stmia r2!, {r1,r3,r8-r9} @ store key_sch[12-15]
152 eor r3, r1 @ key_sch[13]^key_sch[20]
153 eor r8, r3 @ key_sch[14]^key_sch[21]
155 stmia r2!, {r1,r3,r8-r9} @ store key_sch[20-23]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/TransformFunctions/
Darm_bitreversal2.S93 ADDS r3,r1,#1
96 LSRS r3,r3,#1
111 SUBS r3,r3,#1
118 ADDS r3,r1,#1
121 LSRS r3,r3,#1
134 SUBS r3,r3,#1
143 ADDS r3,r1,#1
144 CMP r3,#1
149 LSRS r3,r3,#2
176 SUBS r3,r3,#1
[all …]
Darm_cfft_radix8_f16.c58 float16_t r1, r2, r3, r4, r5, r6, r7, r8; in arm_radix8_butterfly_f16() local
87 r3 = pSrc[2 * i3] + pSrc[2 * i7]; in arm_radix8_butterfly_f16()
91 t1 = r1 - r3; in arm_radix8_butterfly_f16()
92 r1 = r1 + r3; in arm_radix8_butterfly_f16()
93 r3 = r2 - r4; in arm_radix8_butterfly_f16()
113 pSrc[2 * i3 + 1] = t2 - r3; in arm_radix8_butterfly_f16()
114 pSrc[2 * i7 + 1] = t2 + r3; in arm_radix8_butterfly_f16()
188 r3 = pSrc[2 * i3] + pSrc[2 * i7]; in arm_radix8_butterfly_f16()
192 t1 = r1 - r3; in arm_radix8_butterfly_f16()
193 r1 = r1 + r3; in arm_radix8_butterfly_f16()
[all …]
Darm_cfft_radix8_f32.c56 float32_t r1, r2, r3, r4, r5, r6, r7, r8; in arm_radix8_butterfly_f32() local
85 r3 = pSrc[2 * i3] + pSrc[2 * i7]; in arm_radix8_butterfly_f32()
89 t1 = r1 - r3; in arm_radix8_butterfly_f32()
90 r1 = r1 + r3; in arm_radix8_butterfly_f32()
91 r3 = r2 - r4; in arm_radix8_butterfly_f32()
111 pSrc[2 * i3 + 1] = t2 - r3; in arm_radix8_butterfly_f32()
112 pSrc[2 * i7 + 1] = t2 + r3; in arm_radix8_butterfly_f32()
186 r3 = pSrc[2 * i3] + pSrc[2 * i7]; in arm_radix8_butterfly_f32()
190 t1 = r1 - r3; in arm_radix8_butterfly_f32()
191 r1 = r1 + r3; in arm_radix8_butterfly_f32()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/gcc/
Dstartup_MIMXRT1171.S303 ldr r3, =0
307 stmia r4 !, { r0 - r3 }
308 stmia r4 !, { r0 - r3 }
309 stmia r4 !, { r0 - r3 }
310 stmia r4 !, { r0 - r3 }
311 stmia r4 !, { r0 - r3 }
312 stmia r4 !, { r0 - r3 }
313 stmia r4 !, { r0 - r3 }
314 stmia r4 !, { r0 - r3 }
315 stmia r4 !, { r0 - r3 }
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/gcc/
Dstartup_MIMXRT1172.S303 ldr r3, =0
307 stmia r4 !, { r0 - r3 }
308 stmia r4 !, { r0 - r3 }
309 stmia r4 !, { r0 - r3 }
310 stmia r4 !, { r0 - r3 }
311 stmia r4 !, { r0 - r3 }
312 stmia r4 !, { r0 - r3 }
313 stmia r4 !, { r0 - r3 }
314 stmia r4 !, { r0 - r3 }
315 stmia r4 !, { r0 - r3 }
[all …]
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/RTOS2/RTX/Source/
Drtx_core_ca.h434 strexb r3,r1,[r2] in atomic_wr8()
435 cmp r3,#0 in atomic_wr8()
480 strex r3,r0,[r2] in atomic_set32()
481 cmp r3,#0 in atomic_set32()
529 strex r3,r4,[r2] in atomic_clr32()
530 cmp r3,#0 in atomic_clr32()
585 strex r3,r4,[r2] in atomic_chk32_all()
586 cmp r3,#0 in atomic_chk32_all()
648 strex r3,r4,[r2] in atomic_chk32_any()
649 cmp r3,#0 in atomic_chk32_any()
[all …]
Drtx_core_cm.h469 strexb r3,r1,[r2] in atomic_wr8()
470 cbz r3,%F2 in atomic_wr8()
517 strex r3,r0,[r2] in atomic_set32()
518 cbz r3,%F2 in atomic_set32()
577 strex r3,r4,[r2] in atomic_clr32()
578 cbz r3,%F2 in atomic_clr32()
644 strex r3,r4,[r2] in atomic_chk32_all()
645 cbz r3,%F3 in atomic_chk32_all()
718 strex r3,r4,[r2] in atomic_chk32_any()
719 cbz r3,%F3 in atomic_chk32_any()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/gcc/
Dstartup_MIMXRT1011.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/gcc/
Dstartup_MIMXRT1015.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/gcc/
Dstartup_MIMXRT1051.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/gcc/
Dstartup_MIMXRT1024.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/gcc/
Dstartup_MIMXRT1052.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/gcc/
Dstartup_MIMXRT1021.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/gcc/
Dstartup_MIMXRT1061.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/gcc/
Dstartup_MIMXRT1042.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/gcc/
Dstartup_MIMXRT1041.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/gcc/
Dstartup_MIMXRT1062.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/gcc/
Dstartup_MIMXRT1064.S322 ldr r3, =__data_end__
328 subs r3, r2
331 subs r3, #4
332 ldr r0, [r1, r3]
333 str r0, [r2, r3]
338 cmp r2, r3
346 ldr r3, =__ram_function_end__
351 subs r3, r2
354 subs r3, #4
355 ldr r0, [r1, r3]
[all …]
/hal_nxp-latest/mcux/mcux-sdk/utilities/misc_utilities/
Dfsl_memcpy.S203 ands r3, r1, #3 /* Make src 4-byte align. */
212 ands r3, r0, #3 /* Check dest 4-byte align. */
225 lsls r3, r2, #28
230 lsls r3, r2, #29
235 lsls r3, r2, #30
240 lsls r3, r2, #31
247 lsls r3, r0, #31
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54114/gcc/
Dstartup_LPC54114_cm0plus.S119 ldrh r3, [r6, #18] /* Mask for CPU ID bits */
120 cmp r3, r2 /* Core ID matches M4 identifier */
128 ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */
130 ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
135 eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */
184 ldr r3, =__data_end__
186 subs r3, r2
190 subs r3, 4
191 ldr r0, [r1,r3]
192 str r0, [r2,r3]

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