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Searched refs:pll1Config (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/drivers/
Dfsl_clock.c3110 status = CLOCK_SetPbeMode(pllcs, &config->pll1Config); in CLOCK_SetMcgConfig()
3170 if ((config->pll1Config.enableMode & kMCG_PllEnableIndependent) != 0U) in CLOCK_SetMcgConfig()
3172 CLOCK_EnablePll1(&config->pll1Config); in CLOCK_SetMcgConfig()
Dfsl_clock.h690 mcg_pll_config_t pll1Config; /*!< MCGPLL1CLK configuration. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/drivers/
Dfsl_clock.c3110 status = CLOCK_SetPbeMode(pllcs, &config->pll1Config); in CLOCK_SetMcgConfig()
3170 if ((config->pll1Config.enableMode & kMCG_PllEnableIndependent) != 0U) in CLOCK_SetMcgConfig()
3172 CLOCK_EnablePll1(&config->pll1Config); in CLOCK_SetMcgConfig()
Dfsl_clock.h690 mcg_pll_config_t pll1Config; /*!< MCGPLL1CLK configuration. */ member